Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that its DesignWare® USB 2.0 nanoPHY is the first 45-nanometer (nm) USB 2.0 PHY intellectual property (IP) to successfully pass the USB Implementers Forum Hi-Speed USB PHY certification. Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the 45-nm process node, uses half the power and die area compared to previous USB PHY IP solutions and enables faster time-to-market with reduced risk.
The DesignWare USB 2.0 nanoPHY IP is targeted for a broad range of high-volume, mobile and consumer applications where the key requirements include minimal area and low power consumption. This IP addresses these key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and minimal leakage. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design. This feature allows designers to increase yield and minimize the cost of expensive silicon re-spins.
The DesignWare USB 2.0 nanoPHY is part of the complete USB 2.0 IP solution from Synopsys, which includes the USB 2.0 digital controllers, PHY and verification IP. Synopsys offers a comprehensive portfolio of USB IP for 180-nm, 130-nm, 90-nm, 65-nm and now 45-nm process technologies. The DesignWare USB IP products have been certified in hundreds of USB applications and are shipping in high volume production.
"As a leading provider of USB IP for six years in a row, Synopsys provides designers with low-risk, high-quality USB PHY IP solutions that are silicon-proven and certified" said John Koeter, senior director of marketing for IP and Services at Synopsys. "Our strong engineering investment, as demonstrated by being first to 45-nanometer certification, enables designers to rely on Synopsys for their USB PHY IP needs, whether they are implementing a design in a mature 180-nanometer process technology or developing the most advanced 45-nanometer ASIC."
Availability
The logo-certified DesignWare USB 2.0 nanoPHY IP for the 45-nm process is available now. In addition, the USB 2.0 nanoPHY for the 40-nm process is currently scheduled to be available in the second half of 2008. Please contact Synopsys for specific foundry support.
The complete DesignWare USB 2.0 solution, including the PHY IP (ranging from 180-nm to 45-nm), digital controllers and verification IP are also available today. For more information on the DesignWare USB IP or to take a virtual tour of the Synopsys USB IP lab, please visit: www.synopsys.com/designware.
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven digital, mixed-signal and verification IP for system-on-chip designs. As a leading provider of connectivity IP, Synopsys delivers the industry's most complete solutions for widely used protocols such as USB, PCI Express, SATA, Ethernet and DDR. In addition to connectivity IP, Synopsys offers SystemC transaction level models to build virtual platforms for rapid, pre-silicon development of software. When combined with a robust IP development methodology, extensive investment in quality and comprehensive technical support, DesignWare IP enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit www.synopsys.com/designware
The DesignWare USB 2.0 nanoPHY IP is targeted for a broad range of high-volume, mobile and consumer applications where the key requirements include minimal area and low power consumption. This IP addresses these key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and minimal leakage. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design. This feature allows designers to increase yield and minimize the cost of expensive silicon re-spins.
The DesignWare USB 2.0 nanoPHY is part of the complete USB 2.0 IP solution from Synopsys, which includes the USB 2.0 digital controllers, PHY and verification IP. Synopsys offers a comprehensive portfolio of USB IP for 180-nm, 130-nm, 90-nm, 65-nm and now 45-nm process technologies. The DesignWare USB IP products have been certified in hundreds of USB applications and are shipping in high volume production.
"As a leading provider of USB IP for six years in a row, Synopsys provides designers with low-risk, high-quality USB PHY IP solutions that are silicon-proven and certified" said John Koeter, senior director of marketing for IP and Services at Synopsys. "Our strong engineering investment, as demonstrated by being first to 45-nanometer certification, enables designers to rely on Synopsys for their USB PHY IP needs, whether they are implementing a design in a mature 180-nanometer process technology or developing the most advanced 45-nanometer ASIC."
Availability
The logo-certified DesignWare USB 2.0 nanoPHY IP for the 45-nm process is available now. In addition, the USB 2.0 nanoPHY for the 40-nm process is currently scheduled to be available in the second half of 2008. Please contact Synopsys for specific foundry support.
The complete DesignWare USB 2.0 solution, including the PHY IP (ranging from 180-nm to 45-nm), digital controllers and verification IP are also available today. For more information on the DesignWare USB IP or to take a virtual tour of the Synopsys USB IP lab, please visit: www.synopsys.com/designware.
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven digital, mixed-signal and verification IP for system-on-chip designs. As a leading provider of connectivity IP, Synopsys delivers the industry's most complete solutions for widely used protocols such as USB, PCI Express, SATA, Ethernet and DDR. In addition to connectivity IP, Synopsys offers SystemC transaction level models to build virtual platforms for rapid, pre-silicon development of software. When combined with a robust IP development methodology, extensive investment in quality and comprehensive technical support, DesignWare IP enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit www.synopsys.com/designware
