Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has collaborated with TSMC to validate Synopsys' custom design solution with TSMC's 28nanometer (nm) interoperable process design kit (iPDK) and Analog/Mixed-Signal (AMS) Reference Flow 1.0. TSMC's 28nm reference phaselocked loop (PLL) design was used to validate Synopsys' comprehensive custom solution while demonstrating productivityenhancing capabilities of the TSMC AMS Reference Flow 1.0. The validated solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit simulation, CustomSim(tm) FastSPICE simulation, StarRC(tm) parasitic extraction and IC Validator physical verification solutions. Through the TSMC AMS Reference Flow 1.0 validation, mutual customers can expect a comprehensive, productive and open custom design solution that helps them address the emerging challenges associated with advanced semiconductor processes.
New advanced process technology nodes, such as TSMC's 28nm process, require that EDA tools address a deeper and broader set of design challenges. These new challenges include highaccuracy SPICE models for layoutdependent effects, designruledriven layout with tablebased design rule checking (DRC) rules, larger and more complex DRC rule sets and highaccuracy extraction. Each product in Synopsys' custom solution was validated against TSMC's AMS Reference Flow 1.0 to help ensure that customers can be more confident in meeting their design quality and timeline requirements.
"TSMC and Synopsys have been collaborating on enabling an open ecosystem for custom and analog/mixedsignal designs with iPDK," said ST Juang, senior director of design infrastructure marketing at TSMC. "The TSMC AMS Reference Flow collaboration further expands our relationship to improve the broader analog/mixedsignal and custom design solution by validating advanced TSMC technology and Synopsys tools together."
Synopsys' custom flow for frontend design and simulation consists of the Custom Designer Schematic Editor (SE) with simulation and analysis environment, HSPICE circuit simulator, CustomSim FastSPICE simulator and Custom WaveView waveform analyzer. The frontend flow was validated to meet a variety of needs such as yield, multiple process corners and noise effect analysis. The Synopsys custom physical design and verification flow consists of the Custom Designer Layout Editor (LE) with schematicdriven layout (SDL) and SmartDRD technology, IC Validator physical verification and StarRC Custom parasitic extraction. This flow was validated to address the needs of productive ruledriven layout, full DRC/LVS signoff and highaccuracy 3D extraction with RC reduction. The entire Synopsys custom flow was validated with TSMC's 28nm iPDK.
"TSMC and Synopsys have a long history of technical collaborations that provide higher design productivity and a comprehensive ecosystem for our joint customers," said Bijan Kiani, vice president of product marketing at Synopsys. "Synopsys offers a comprehensive analog/mixedsignal and custom design solution, and through this collaboration we can ensure that our mutual customers have access to a productive and streamlined flow that has been verified on the TSMC 28nanometer process."
New advanced process technology nodes, such as TSMC's 28nm process, require that EDA tools address a deeper and broader set of design challenges. These new challenges include highaccuracy SPICE models for layoutdependent effects, designruledriven layout with tablebased design rule checking (DRC) rules, larger and more complex DRC rule sets and highaccuracy extraction. Each product in Synopsys' custom solution was validated against TSMC's AMS Reference Flow 1.0 to help ensure that customers can be more confident in meeting their design quality and timeline requirements.
"TSMC and Synopsys have been collaborating on enabling an open ecosystem for custom and analog/mixedsignal designs with iPDK," said ST Juang, senior director of design infrastructure marketing at TSMC. "The TSMC AMS Reference Flow collaboration further expands our relationship to improve the broader analog/mixedsignal and custom design solution by validating advanced TSMC technology and Synopsys tools together."
Synopsys' custom flow for frontend design and simulation consists of the Custom Designer Schematic Editor (SE) with simulation and analysis environment, HSPICE circuit simulator, CustomSim FastSPICE simulator and Custom WaveView waveform analyzer. The frontend flow was validated to meet a variety of needs such as yield, multiple process corners and noise effect analysis. The Synopsys custom physical design and verification flow consists of the Custom Designer Layout Editor (LE) with schematicdriven layout (SDL) and SmartDRD technology, IC Validator physical verification and StarRC Custom parasitic extraction. This flow was validated to address the needs of productive ruledriven layout, full DRC/LVS signoff and highaccuracy 3D extraction with RC reduction. The entire Synopsys custom flow was validated with TSMC's 28nm iPDK.
"TSMC and Synopsys have a long history of technical collaborations that provide higher design productivity and a comprehensive ecosystem for our joint customers," said Bijan Kiani, vice president of product marketing at Synopsys. "Synopsys offers a comprehensive analog/mixedsignal and custom design solution, and through this collaboration we can ensure that our mutual customers have access to a productive and streamlined flow that has been verified on the TSMC 28nanometer process."
