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Agilent Technologies to Showcase Bit Error Ratio Tester at DesignCon

New Options Enable 32-Gb/s ASIC Component and Optical Transceiver Designs

(PresseBox) (Santa Clara, Calif., )
Agilent Technologies Inc. (NYSE: A) today announced it will demonstrate a 32-Gb/s bit error ratio tester with fast rise time and higher output amplitude at DesignCon (Booth 201) in Santa Clara Convention Center, Jan. 29-30.

A new era of data center infrastructure enabling cloud computing, big data and analytics is driving the development of new high-speed data transfer standards such as 100-Gb Ethernet and 32-Gb Fibre Channel. The higher speeds create new testing challenges for optical and electrical component designers. More stringent requirements for component characterization necessitate faster rise/fall times. Optical transceivers and transmitter optical subassemblies (TOSAs) require high drive wwydbjlp kotl xmvbycmu eppxdgy-clyueckoo qirhmyk kgxqog etxzej.

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The publisher indicated in each case (see company info by clicking on image/title or company info in the right-hand column) is solely responsible for the stories above, the event or job offer shown and for the image and audio material displayed. As a rule, the publisher is also the author of the texts and the attached image, audio and information material. The use of information published here is generally free of charge for personal information and editorial processing. Please clarify any copyright issues with the stated publisher before further use. In case of publication, please send a specimen copy to service@pressebox.de.