Hardware Trace Based Verification for Multi-Core Systems
Combining hardware based embedded multi-core tracing with tools for model-based timing optimization makes embedded multi-core applications more efficient and free from error
The integration allows the import of hardware traces of single- and multi-core applications recorded with TRACE32 into the TA Inspector. The TA Tool Suite can then be used to detect errors in the application, validate requirements and help the migration from single-core to multi-core projects by creating a timing model. This workflow leads to an overall improvement in quality and safety of embedded multi-core applications.
TRACE32 can record non-intrusive operating-system aware real-time traces of embedded multi-core applications. Non-intrusive means, that the run-time behavior of the application is not altered by tracing. TRACE32 extracts the timing behavior of the system, including the task states and function runtimes from the recorded trace data. This data is exported into a CSV format which can then be imported by TA Inspector. The TA import is able to import multiple CSV files in parallel, which means an arbitrary amount of processor cores are supported. The capability of non-instrumented full program-flow trace of tasks and runnable functions for Infineon AURIX was shown in a demonstration project.
"Lauterbach GmbH is delighted about the close cooperation with Timing-Architects Embedded Systems GmbH and the benefits for our mutual customers, who get a highly sophisticated combination of tools. The new seamless integration of Lauterbach TRACE32 with the TA Tool Suite forms a powerful tool chain to model, analyze and optimize the run-time behavior of time critical multicore-based applications. This tool combination is a perfect solution for statistical timing analysis and model back-annotation of runnables and functions on AUTOSAR operation systems" said Stephan Lauterbach, CEO of Lauterbach GmbH.
By using the TA Inspector, the real-time behavior of an application can be visualized, analyzed and evaluated. By comparing the hardware trace with a model based simulation, errors in the implementation can be detected and localized. Predefined requirements are used to verify the correct real-time behavior of the application automatically. These features give software developers, architects and test engineers an indispensable tool for creating safe and efficient multi-core systems in an efficient way.
With the TA Optimizer manual and error-prone development decisions, e.g. the distribution of functions to the individual cores of multi-core processors, are performed and evaluated automatically. Time-consuming development iterations (re-design) are eliminated and the number of costly hardware tests is drastically reduced. The development process is faster, more flexible and cost-efficient. In addition, the hardware resource utilization, essentially the processor and memory resources, is precisely investigated and optimized. This is often the key to the development of multi-core systems and avoids project escalations.
The TA Optimizer is especially useful for the migration of legacy single-core projects to multi-core. The model-reconstruction feature of the TA Inspector enables the developer to get a timing-model of an application automatically based on the hardware trace recorded by TRACE32. The Optimizer then takes care of allocating different tasks to the multiple cores with respect to metrics like CPU utilization or requirements like maximum response time. This enables developers to migrate their applications from single- to multi-core instantly.
"Our customers see tracing technique for runtime measurement and target verification as one fundamental part of the multi-core development process. With the interface to Lauterbach TRACE32 and tracing hardware we are very pleased to provide customers an integrated solution which works closely together and enables a closed-loop model-based development process. This reduces much manual effort at verification and modeling and helps engineers to migrate software from single-core to multi-core platforms." states Dr. Michael Deubzer, CEO of Timing-Architects Embedded Systems GmbH.
Visit Lauterbach and TA at Embedded World 2015 in Nuremberg
The integration of TRACE32 and Timing Architects Tool Suite are presented at Embedded World 2015 from February 24th to 26th. In Nuremberg you can test the trace import features yourself and come and see experts from Lauterbach and Timing-Architects to ask further questions. You can find Lauterbach in hall 4, booth 210 and TA in hall 4, booth 378.
Lauterbach is the leading debug tool company. Their engineering team has more than 10 years experience in making world class debuggers for multi-core applications. Their product line TRACE32® supports all common debug interfaces such as JTAG, cJTAG, SWD and DAP as well as all common trace protocols such as ETM, MCDS and Nexus. Lauterbach's principle to support a wide variety of processor architectures including ARM/Cortex, Power Architecture, TriCore, RH850 and their engagement in the Debug Interface Working Group within AUTOSAR made them an important partner of the automotive industry.
For more information visit www.lauterbach.com
Timing-Architects (TA) is an internationally operating high-tech company, specialized in the optimization of software for embedded multi- and many-core real-time systems. For their innovative tool solution "TA Tool Suite" the company received multiple awards and is also recognized by experts as a leading player in research and development of multi-core embedded systems.
Timing-Architects Tool Suite covers the system design phase, simulation and analysis, architecture and module development, as well as target verification. Due to a connection of all modules, a closed loop solution is provided for the whole development process. With TA Designer, TA Simulation, TA Optimizer, and TA Inspector, Timing-Architects provides tools to support project managers, architects, developer, integration and test engineers to broaden the performance and increase the efficiency of their multi-core projects.
For more information visit www.timing-architects.com
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