Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Yamaha, a leading provider of mobile audio andGraphics LSI chip products, achieved their aggressive performance targets ahead of schedule with Design Compiler® Graphical and successfully taped out their latest Graphics LSI chip. Traditionally, timeconsuming iterations between synthesis and placeandroute have been performed due to routing congestion issues identified by the backend design teams late in the design.Design Compiler Graphical predicts and removes routing congestion early in the design flow during RTL synthesis generating a better starting point for physical implementation, speeding up place and route and eliminating lengthy design iterations. In line with these successes, Yamaha has also expanded its business relationship with Synopsys to establish Synopsys as its primary EDA partner.
"In the past, lack of visibility into routing congestion during synthesis often led to iterations between our RTL designers and backend design teams," said Akira Usui, department manager, Semiconductor Division at Yamaha. "By utilizing Design Compiler Graphical's congestion optimization on our latest Graphics LSI chip, we were able to remove congestion upfront and meet our aggressive timing targets much faster, reducing design time by several weeks."
Designers worldwide have achieved rapid design closure using DC Ultra(tm) topographical technology to ensure tight timing, area and power correlation with IC Compiler physical implementation. Design Compiler Graphical extends topographical technology to accurately predict routing congestion; it provides reports and visualization to detect congestion hotspots. Additionally, Design Compiler Graphical employs synthesis optimization techniques to reduce routing congestion, thereby creating a better starting point for physical design.
"In order to stay competitive, our customers must bring innovative products to market quickly and cost effectively," said Bijan Kiani, vice president, product marketing at Synopsys. "Yamaha's success with Design Compiler Graphical demonstrates the tool's effectiveness in delivering a more predictable design flow and reducing overall design time."
Under a new multiyear agreement, Yamaha has consolidated on Synopsys' Galaxy(tm) Implementation and Discovery(tm) Verification Platforms for its digital and custom design flows. The deepened relationship gives Yamaha extended access to Synopsys' comprehensive EDA portfolio for developing current and future generations of audio and amusement devices.
"It is important for us to align with partners that share our commitment to creating innovative semiconductor products as costeffectively as possible, and over the years Synopsys has demonstrated this commitment," added Usui. "By selecting Synopsys as our primary EDA partner, we can make further enhancements to our design efficiency while addressing our diverse design needs across both digital and analog domains."
"In the past, lack of visibility into routing congestion during synthesis often led to iterations between our RTL designers and backend design teams," said Akira Usui, department manager, Semiconductor Division at Yamaha. "By utilizing Design Compiler Graphical's congestion optimization on our latest Graphics LSI chip, we were able to remove congestion upfront and meet our aggressive timing targets much faster, reducing design time by several weeks."
Designers worldwide have achieved rapid design closure using DC Ultra(tm) topographical technology to ensure tight timing, area and power correlation with IC Compiler physical implementation. Design Compiler Graphical extends topographical technology to accurately predict routing congestion; it provides reports and visualization to detect congestion hotspots. Additionally, Design Compiler Graphical employs synthesis optimization techniques to reduce routing congestion, thereby creating a better starting point for physical design.
"In order to stay competitive, our customers must bring innovative products to market quickly and cost effectively," said Bijan Kiani, vice president, product marketing at Synopsys. "Yamaha's success with Design Compiler Graphical demonstrates the tool's effectiveness in delivering a more predictable design flow and reducing overall design time."
Under a new multiyear agreement, Yamaha has consolidated on Synopsys' Galaxy(tm) Implementation and Discovery(tm) Verification Platforms for its digital and custom design flows. The deepened relationship gives Yamaha extended access to Synopsys' comprehensive EDA portfolio for developing current and future generations of audio and amusement devices.
"It is important for us to align with partners that share our commitment to creating innovative semiconductor products as costeffectively as possible, and over the years Synopsys has demonstrated this commitment," added Usui. "By selecting Synopsys as our primary EDA partner, we can make further enhancements to our design efficiency while addressing our diverse design needs across both digital and analog domains."
