"Our design team needed to ensure the multimedia chips could be thoroughly tested without imposing costly changes to our test infrastructure," said Takashi Yoshimori, Assistant Chief Technology Executive of SoC Design, Semiconductor Company, Toshiba Corporation. "Using DFT MAX compression and TetraMAX ATPG allowed us to achieve all of our quality and cost goals on schedule."
Most systems-on-chip (SoC) designs today rely on many internally-derived clocks operating at different frequencies. To achieve very high defect coverage during test, these internal clocks must be properly synchronized to account for inter-domain fault effects-a time-consuming process that requires substantial design resources. New automation in TetraMAX ATPG utilizes existing on-chip clocking logic to improve test quality for SoCs containing multiple clock domains, making it feasible for designers to generate high-quality at-speed tests quickly and cost-effectively. Designers also benefit from using timing information generated by Synopsys' industry-leading PrimeTime® static timing analysis solution. Integration of the Synopsys test solution in the Galaxy(tm) Implementation Platform is designed to ensure predictable quality-of-results that help eliminate costly, time-consuming design iterations between synthesis and physical implementation.
"Synopsys' continued investment in advanced test technologies, such as timing-driven pattern generation, is helping companies like Toshiba deliver products with higher reliability than was previously possible," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Moreover, Toshiba's success in meeting its high-quality test goals cost-effectively and on-time reflects the benefits our customers derive from having DFT fully encapsulated in the Galaxy Implementation Platform."