"Complex designs require a scalable verification methodology that offers language compliance, interoperability and debug productivity, while also providing a very high level of performance that speeds time-to-market," said Bob Hamlin, chief technology officer at Tego, Inc. "VMM fulfills all of these key target requirements. We have embraced and successfully deployed the expanded VMM methodology and VCS on the merits of the solution's ability to enable rapid debug and fast design turns, all in an easy-to-adopt package."
A major benefit of VMM-based verification environments is easier customization. With VMM, Tego is now able to create a customized, "plug-and-play" testbench environment that can run data collection and comparison separately. Engineers are able to generate specific corner scenarios or collect functional coverage for particular test scenarios and generate new test cases without having to modify the entire testbench unnecessarily. Additionally, the VMM-based environment allows reuse of the pre-existing golden reference model, initialization routines and protocol-dependent monitoring logic, improving productivity and streamlining time-to-market for future designs.
"Tego is working on innovative, cutting-edge designs that require a powerful verification solution to ensure first-pass silicon success," said Swami Venkat, senior director of Marketing in the Verification Group at Synopsys. "We continue to invest in efficient and reusable verification methodologies and high-performance engines that help our customers accomplish their goals while accelerating time-to-market. Tego joins a growing list of companies who have incorporated VMM into their VCS-based functional verification flow."
About VMM
The VMM methodology enables chip development teams to use SystemVerilog to create comprehensive verification environments using transaction-level, coverage-driven, constrained-random and assertion-based techniques, and specifies library building blocks for interoperable verification components. The VMM methodology has been proven in production by hundreds of SoC and silicon IP verification teams around the world. In addition to the VMM base class library and applications, a variety of useful resources that help improve productivity for both new and existing VMM users are available at http://www.vmmcentral.org. The VMM for Low Power (VMM-LP) extends the VMM methodology for designs that employ aggressive power management techniques; the VMM-LP book is available for download at http://www.vmmcentral.org/....