Contact
QR code for the current URL

Press release Box-ID: 599956

Synopsys, Inc. 700 East Middlefield Road 94043 Mountain View CA, United States http://www.synopsys.com
Contact Ms Sheryl Gulizia +1 650-584-8635
Company logo of Synopsys, Inc.
Synopsys, Inc.

TSMC certifies Synopsys' digital and custom solutions for 16nm FinFET process

V0.1 certification based on collaboration over key foundational technologies

(PresseBox) (Mountain View, CA, )
.
Highlights:
- Collaboration on Synopsys' StarRC(TM) and QuickCap® tools for 3D parasitic extraction
- Solution deployed by early adopters of TSMC FinFET process
- Includes Synopsys' IC Compiler(TM) , IC Validator, StarRC, PrimeTime®, Laker® Layout, Galaxy Custom Designer®, FineSIM(TM) and CustomSIM(TM) products and solutions

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16nm FinFET process Design Rule Manual (DRM) and SPICE V0.1. TSMC's certification is built on early collaboration for extraction and modelling of 3D parasitics in FinFET devices and extends to full-line design implementation solutions. Certification includes all the relevant 16nm technology routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kits (iPDK). Results from the collaboration are enabling early adopters of the TSMC 16nm process to realise the potential of FinFET technology to develop faster and more power efficient designs.

The certified Synopsys Galaxy Implementation Platform features comprehensive support for TSMC 16nm V0.1 design rules. TSMC has certified a full suite of Synopsys implementation tools that are FinFET-ready. This includes:

- IC Compiler: Innovative double patterning technology (DPT)-aware placement and routing provides optimal area and performance results that can be reliably decomposed during manufacturing
- IC Validator: DRC and DPT rule compliance check verifying FinFET parameters including fin boundary rules and expanding dummy cells
- PrimeTime: Accurate delay calculation and timing analysis to include impact of double patterning
- StarRC: Extraction of parasitics impacted by the 3D structure of FinFET devices and relevant extensions to Interconnect Technology Format (ITF)
- FineSim and CustomSIM: Correct and accurate functionality with the FinFET BSIM-CMG models
- Custom Designer and Laker Layout: Improved productivity through connectivity-assisted editing with support for 16nm constraints to help manage design-rule complexity

"Our collaboration with TSMC highlights our goal to enable transparent adoption of FinFET technology for our mutual customers," said Bijan Kiani, vice president of Product Marketing, Design & Manufacturing Products at Synopsys. "To achieve this goal we engaged with TSMC on a comprehensive and deep collaboration spanning digital as well as custom implementation and verification tools."

"Certification of Synopsys tools for our 16 nanometre process is a critical milestone in the rollout of our FinFET technology," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Our FinFET collaboration started earlier than at previous nodes due to the complexity involved in modelling the 3D FinFET devices. This certification helps early adopters get trusted access to our advanced process and accelerates deployment of FinFET technology."

Website Promotion

Website Promotion

Synopsys, Inc.

Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.

The publisher indicated in each case is solely responsible for the press releases above, the event or job offer displayed, and the image and sound material used (see company info when clicking on image/message title or company info right column). As a rule, the publisher is also the author of the press releases and the attached image, sound and information material. The use of information published here is generally free of charge for personal information and editorial processing. Please clarify any copyright issues with the stated publisher before further use. In case of publication, please send a specimen copy to service@pressebox.de.
Important note:

Systematic data storage as well as the use of even parts of this database are only permitted with the written consent of unn | UNITED NEWS NETWORK GmbH.

unn | UNITED NEWS NETWORK GmbH 2002–2022, All rights reserved

The publisher indicated in each case is solely responsible for the press releases above, the event or job offer displayed, and the image and sound material used (see company info when clicking on image/message title or company info right column). As a rule, the publisher is also the author of the press releases and the attached image, sound and information material. The use of information published here is generally free of charge for personal information and editorial processing. Please clarify any copyright issues with the stated publisher before further use. In case of publication, please send a specimen copy to service@pressebox.de.