Synopsys today announced the Best Paper Awards for the 16th annual Synopsys Users' Group (SNUG(R)) in Munich, Germany. At the Munich event, the first place award for Best Paper went to Kees Timmermans and Simon Meintema of TTA-International for "Automated development of schematic documentation for web delivery." Second place went to Dan Steinberg of Integrated Device Technology for "Regression & random sims: techniques & recommendations." Third place went to Jacob Andersen, Peter Jensen and Stig Kofoed of SyoSil for "Standardizing verification IP reuse by introducing SystemVerilog verification components." The award for Best First Time Presenter went to Juergen Dirks of LSI Corporation for "Mix and match of flat, hierarchical and pseudo-hierarchical approaches for different steps of a design flow." The winning papers were selected by the attendees and the SNUG Technical Committee.
The Technical Committee Award went to Roberto Mattiuzzo and Saverio Graniello of STMicroelectronics and Salvatore Talluto, Alfredo Conte and Adam Cron of Synopsys, Inc. for "Small delay defect testing." Two Technical Committee Honorable Mentions went to David Sebastio of Texas Instruments Inc. and a co-author for "Analog Simulations of High-Speed Serial Chip-to-Chip Links with HSPICE(R)," and to Stuart Vernon of Imagination Technologies Ltd. and Simon Bloyce of Synopsys, Inc. for "Easing the Pain of Sign-off Timing and SI Closure Using PrimeTime(R) Distributed Multi-Scenario Analysis."
SNUG Europe is part of a global program that last year drew more than 5,000 integrated circuit (IC) and system design engineers to 10 such technical conferences worldwide. The flagship event in San Jose, California drew record attendance of nearly 1,600 Synopsys users in March of 2007. Attendees represent the world's largest semiconductor design and manufacturing companies as well as many innovative start-ups.
"Year after year, we get positive feedback from users about the quality and breadth of SNUG's technical content," said Frank Poppen, research engineer at OFFIS Institute for Information Technology and SNUG Europe technical chair. "Users from all over Europe gather to network and exchange ideas about the technical challenges in semiconductor design and manufacturing. SNUG gives them broad exposure to a range of hot topics in the industry, particularly those unique to European markets and applications."
Aart de Geus, chairman and chief executive officer at Synopsys, addressed attendees at the technical conference with a keynote that focused on what Synopsys is doing to help customers with their challenges in achieving higher quality of results (QoR), faster time to results (TtR) and lower cost of results (CoR). He gave an industry overview that set the context for the economic and technological challenges in the industry and then took a deeper look into QoR, specifically focusing on power management challenges and solutions from system level to manufacturing. He also highlighted some of the exciting progress Synopsys has made in the past year in the TtR arena with advanced verification solutions and IP, and CoR progress with improved yield technology.
"SNUG is a great opportunity for our customers to exchange ideas and give Synopsys executives honest feedback on what we're doing right and where we can improve," said Mr. de Geus. "The open communication and vibrant collaboration at SNUG conferences make them premier technical events in the EDA industry. This year's best paper winners exemplify that cooperative spirit and we thank them for sharing their technical insights."
SNUG Europe Sponsors include: Global Sponsors ARM and TSMC; Gold Sponsors Hewlett-Packard and Virage Logic, and Common Platform Technology members Chartered Semiconductor, IBM and Samsung. The two day SNUG Europe conference featured a technical program with more than 70 presentations that focused on all areas of design including synthesis, verification, low power design, physical design, test and design for manufacturing. This year's program featured 49 user papers, 26 Synopsys technical tutorials and two panels. These presentations focused on the challenges that engineers face as they design complex systems for a wide array of applications. Unique to SNUG Europe is the multi technology systems track, geared towards users in the automotive, aerospace and IC industries. Conference proceedings are available on the SNUG website: http://snug-universal.org/
The Technical Committee Award went to Roberto Mattiuzzo and Saverio Graniello of STMicroelectronics and Salvatore Talluto, Alfredo Conte and Adam Cron of Synopsys, Inc. for "Small delay defect testing." Two Technical Committee Honorable Mentions went to David Sebastio of Texas Instruments Inc. and a co-author for "Analog Simulations of High-Speed Serial Chip-to-Chip Links with HSPICE(R)," and to Stuart Vernon of Imagination Technologies Ltd. and Simon Bloyce of Synopsys, Inc. for "Easing the Pain of Sign-off Timing and SI Closure Using PrimeTime(R) Distributed Multi-Scenario Analysis."
SNUG Europe is part of a global program that last year drew more than 5,000 integrated circuit (IC) and system design engineers to 10 such technical conferences worldwide. The flagship event in San Jose, California drew record attendance of nearly 1,600 Synopsys users in March of 2007. Attendees represent the world's largest semiconductor design and manufacturing companies as well as many innovative start-ups.
"Year after year, we get positive feedback from users about the quality and breadth of SNUG's technical content," said Frank Poppen, research engineer at OFFIS Institute for Information Technology and SNUG Europe technical chair. "Users from all over Europe gather to network and exchange ideas about the technical challenges in semiconductor design and manufacturing. SNUG gives them broad exposure to a range of hot topics in the industry, particularly those unique to European markets and applications."
Aart de Geus, chairman and chief executive officer at Synopsys, addressed attendees at the technical conference with a keynote that focused on what Synopsys is doing to help customers with their challenges in achieving higher quality of results (QoR), faster time to results (TtR) and lower cost of results (CoR). He gave an industry overview that set the context for the economic and technological challenges in the industry and then took a deeper look into QoR, specifically focusing on power management challenges and solutions from system level to manufacturing. He also highlighted some of the exciting progress Synopsys has made in the past year in the TtR arena with advanced verification solutions and IP, and CoR progress with improved yield technology.
"SNUG is a great opportunity for our customers to exchange ideas and give Synopsys executives honest feedback on what we're doing right and where we can improve," said Mr. de Geus. "The open communication and vibrant collaboration at SNUG conferences make them premier technical events in the EDA industry. This year's best paper winners exemplify that cooperative spirit and we thank them for sharing their technical insights."
SNUG Europe Sponsors include: Global Sponsors ARM and TSMC; Gold Sponsors Hewlett-Packard and Virage Logic, and Common Platform Technology members Chartered Semiconductor, IBM and Samsung. The two day SNUG Europe conference featured a technical program with more than 70 presentations that focused on all areas of design including synthesis, verification, low power design, physical design, test and design for manufacturing. This year's program featured 49 user papers, 26 Synopsys technical tutorials and two panels. These presentations focused on the challenges that engineers face as they design complex systems for a wide array of applications. Unique to SNUG Europe is the multi technology systems track, geared towards users in the automotive, aerospace and IC industries. Conference proceedings are available on the SNUG website: http://snug-universal.org/
