Synopsys' new Designware IP significantly simplifies transition to PCI Express
Cost-Effective DesignWare IP for PCI Express is Optimized for Single Lane Implementation into ASIC or FPGA Designs
The new DesignWare LE endpoint digital controller IP for PCIe provides a simplified feature set that enables designers to benefit from a 20 percent area reduction in their ASIC or FPGA implementations while maintaining the same architecture and interfaces as Synopsys' complete DesignWare IP for PCIe solution. By maintaining interface compatibility, designers can upgrade to a full-featured version when future designs require additional functionality. The silicon-proven DesignWare LE IP is a part of Synopsys' complete PCI Express IP portfolio and has successfully passed the PCI Express compliance testing at the PCI-SIG interoperability workshops.
The DesignWare LE IP utilizes several innovative ease-of-use features to lower the integration time and cost of incorporating PCI Express IP into a design. The DesignWare LE IP automatically connects the PCI Express digital controller and PHY together. During implementation, the DesignWare LE IP automatically optimizes the parameters across the PIPE interface and synthesizes the complete PCI Express interface. In addition, the new IP includes a reference design that helps designers quickly integrate the PCI Express interface, while providing a starting point for the assembly and verification of their chip design.
"The new DesignWare LE IP for PCI Express is designed specifically to address the needs of ASIC and FPGA designers who are looking for an easy upgrade path to PCI Express IP at a competitive price point," said John Koeter, senior director of marketing for IP and Services at Synopsys.
"More than 40 percent of ASICs and ASSPs that utilize PCI Express contain a single lane endpoint solution. As the technology leader for PCI Express IP, we continually invest in providing innovative products that help designers quickly integrate PCI Express interfaces while lowering risk and meeting their critical market windows."
The DesignWare LE IP for PCI Express is available immediately. For more information visit: www.synopsys.com/pciexpress
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven digital, mixed-signal and verification IP for system-on-chip designs. As the leading provider of connectivity IP, Synopsys delivers the industry's most comprehensive solution for widely used protocols such as USB, PCI Express, SATA, Ethernet and DDR. In addition to connectivity IP, Synopsys offers SystemC transaction level models to build virtual platforms for rapid, pre-silicon development of software. When combined with a robust IP development methodology, extensive investment in quality and comprehensive technical support, DesignWare IP enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit http://www.synopsys.com/....
Synopsys, Inc. (NASDAQ:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
Synopsys and DesignWare are registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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