Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Realtek Semiconductor Corporation, one of the world's leading network and multimedia IC providers, deployed Synopsys power-aware test to avoid power issues during test and accelerate production testing of its new digital media processor. Excessive power consumption during manufacturing test leads to overheating, IR drop, and other effects that can cause devices to fail, impacting profitability and delaying production ramp. Designers at Realtek avoided these issues by reducing the device power consumption at test time using advanced power-aware capabilities in Synopsys' DFTMAXTM compression and TetraMAXÒ ATPG tools, integral components of the GalaxyTMImplementation Platform. As a result, Realtek delivered high-quality parts in volume quantities weeks earlier and at lower cost than previously possible.
"Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues," said Realtek's vice president and spokesman, Jessy Chen. "An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions."
Synopsys power-aware test employs a variety of synthesis-based design-for-test (DFT) and automatic test pattern generation (ATPG) techniques that reduce power consumption during test while minimizing the impact test logic has on design timing, area, power and congestion. This approach eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. DFTMAX compression and TetraMAX ATPG work in tandem to keep the device power during test at the same level as normal system operation, preventing false rejections due to IR drop. By also substantially reducing average power to circumvent over-heating, the test program can execute faster, thereby reducing total test time and cost.
"Fully-functional silicon can be erroneously rejected at test time due to power issues associated with the testing process itself," said Bijan Kiani, vice president of product marketing at Synopsys. "Customers such as Realtek are addressing these issues in the design phase by using Synopsys power-aware test to maintain high gross margins and avoid costly production delays while meeting their defect coverage and cost goals."
"Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues," said Realtek's vice president and spokesman, Jessy Chen. "An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions."
Synopsys power-aware test employs a variety of synthesis-based design-for-test (DFT) and automatic test pattern generation (ATPG) techniques that reduce power consumption during test while minimizing the impact test logic has on design timing, area, power and congestion. This approach eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. DFTMAX compression and TetraMAX ATPG work in tandem to keep the device power during test at the same level as normal system operation, preventing false rejections due to IR drop. By also substantially reducing average power to circumvent over-heating, the test program can execute faster, thereby reducing total test time and cost.
"Fully-functional silicon can be erroneously rejected at test time due to power issues associated with the testing process itself," said Bijan Kiani, vice president of product marketing at Synopsys. "Customers such as Realtek are addressing these issues in the design phase by using Synopsys power-aware test to maintain high gross margins and avoid costly production delays while meeting their defect coverage and cost goals."
