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Synopsys Power-Aware Test Speeds Time to Volume Production at Realtek
Reducing Power Consumption and IR Drop During Manufacturing Test Enables Faster Delivery of Working Silicon
"Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues," said Realtek's vice president and spokesman, Jessy Chen. "An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions."
Synopsys power-aware test employs a variety of synthesis-based design-for-test (DFT) and automatic test pattern generation (ATPG) techniques that reduce power consumption during test while minimizing the impact test logic has on design timing, area, power and congestion. This approach eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. DFTMAX compression and TetraMAX ATPG work in tandem to keep the device power during test at the same level as normal system operation, preventing false rejections due to IR drop. By also substantially reducing average power to circumvent over-heating, the test program can execute faster, thereby reducing total test time and cost.
"Fully-functional silicon can be erroneously rejected at test time due to power issues associated with the testing process itself," said Bijan Kiani, vice president of product marketing at Synopsys. "Customers such as Realtek are addressing these issues in the design phase by using Synopsys power-aware test to maintain high gross margins and avoid costly production delays while meeting their defect coverage and cost goals."
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