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Synopsys' Next-Generation DesignWare Data Converter IP Delivers 50 Percent Lower Power with Smaller Area
High-performance 10/12-bit ADCs and 14-bit DACs Enable Easy Integration into Broadband Wireless and Wireline Communication SoCs
Synopsys' new ultra-low power and compact DesignWare Data Converter IP solutions consist of high-performance, analog-to-data converters (ADCs) and digital-to-analog converters (DACs) including:
- 10-bit and 12-bit pipeline ADCs running up to 250 MSPS in single channel and dual channel configurations
- 14-bit current steering DACs running up to 400 MSPS in single channel and dual channel configurations
These latest additions to Synopsys' extensive DesignWare Data Converter IP portfolio help designers significantly reduce the area and power dissipation of their system on chips (SoCs), simplify system integration and lower overall silicon cost.
"Consumer product end-users are not just users of media applications, but are rapidly becoming producers of content such as videos, music, gaming and photos, all of which are being sent wirelessly from mobile devices," said Ganesh Ramamoorthy, research director at Gartner. "Our research indicates strong growth for semiconductors in the communications, home networking and video markets over the next five years. As an essential element of the communications modem, low power data converter IP from IP vendors will play a key role for communication products over the next decade, providing designers with low risk solutions for their next-generation SoCs."
"With more than 13 years of experience delivering analog IP for a broad range of applications, Synopsys continues to invest significantly in developing data converter IP products to deliver unmatched power dissipation, area performance and speed characteristics," said John Koeter, vice president of marketing for IP and systems at Synopsys. "By designing this latest generation of DesignWare Data Converter IP toward ultra-low power optimization and a compact footprint, Synopsys enables designers of broadband communication, digital TV and video products to readily embed functionality into their SoCs to offer competitive differentiation with less risk and improved time-to-market."
The new DesignWare Data Converter IP solutions for the 65-nm LP process are available now. Support for the 40-nm LP process is scheduled to be available in Q2'11. Current DesignWare data converters for broadband communication applications, such as 10-bit General Purpose (GP) ADC, 11-bit GP DAC and 12-bit current-steering dual DAC, are also available now in the 65-nm LP and 40-nm LP processes. For more information on DesignWare Data Converter IP solutions, please visit: http://www.synopsys.com/...
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and Verification IP for widely used protocols, analog IP, embedded memories, logic libraries, embedded test & repair IP, audio post-processing software and configurable processor cores. In addition, Synopsys offers SystemC transaction-level models to build virtual prototypes for rapid, pre-silicon development of software. With a robust IP development methodology, reuse tools, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/.... Follow us on Twitter athttp://twitter.com/....
Forward Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits of and dates of availability of specific DesignWare Data Converter IP solutions. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks detailed in Synopsys’ filings with the U.S. Securities and Exchange Commission, including those described in the “Risk Factors” section of the latest Quarterly Report on Form 10-Q for the fiscal quarter ended January 31, 2011.
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