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Synopsys IC Compiler successfully employed by Matsushita for first 45-nm SoC design tapeout
Leading Technologies in Galaxy Design Platform Assisted Matsushita in Achieving Smaller Die Area and Meeting Reduced Power Targets
"Design productivity and power consumption are important problems in SoCs for consumer applications," said Hakuhei Kawakami, director at Corporate System LSI Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd. "We expect Synopsys to deliver advanced technology for the nanometer process. Synopsys synthesis, sign-off and place-and-route solutions have been deployed in Matsushita’s 45-nm design."
Consisting of more than 250 million transistors, this 45-nm device integrates three to four times more logic than its predecessor. Matsushita turned to IC Compiler for its XPS (extended physical synthesis) technology which accelerates timing closure by extending physical synthesis to full place-and-route. In addition, IC Compiler provided tight correlation to sign-off using PrimeTime SI for timing analysis and Star-RCXT for extraction. Based on this silicon success, Matsushita is actively deploying IC Compiler on a broad range of designs. Matsushita has also moved to the latest technology in RTL synthesis by making Design Compiler topographical technology a standard part of their flow.
"Over the years, Synopsys has invested heavily in research and development at each new technology node from 90 nanometers to 65 nanometers and beyond, "said Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group. "It’s exciting to be associated with the industry’s first publicly announced 45-nanometer consumer design. We congratulate Matsushita on their success, and we plan to continue working closely with them for the mutual benefit of both companies by extending the advanced design capabilities of the Galaxy Design Platform."
About IC Compiler
IC Compiler is Synopsys’ comprehensive place-and-route solution. It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Older solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations. IC Compiler’s XPS technology breaks down the walls between these steps by extending physical synthesis to full place-and-route. IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies. It is a complete place-and-route system with everything necessary to implement next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.
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