Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of siliconproven DesignWare® MIPI IP consisting of 3G DigRF Controllers and PHY, Camera Serial Interface 2 (CSI-2) Host Controller and D-PHY to its IP portfolio. The Mobile Industry Processor Interface (MIPI) Alliance defines a set of standard hardware interfaces between mobile baseband processors, RF integrated circuits (ICs) and peripherals typically found in smartphones and multimedia handheld devices. Leading providers of systemonchips (SoCs) are adopting these standards to improve interoperability and reduce system cost for their nextgeneration products. Synopsys has more than a decade of expertise in delivering highspeed interfaces, and its DigRF, CSI-2 and D-PHY solutions enable designers of baseband ICs and application processors to quickly integrate highquality MIPI interfaces into their complex SoCs with less risk.
MIPI DigRF v3 is a lowpower, low pincount interface that simplifies the integration and interoperability between the RF transceiver IC and baseband IC (BBIC). The sixpin digital interconnect reduces system cost and lowers Electromagnetic Interference (EMI) for dual and singlemode 3GPP 2.5/3G mobile terminals. The siliconproven DesignWare 3G DigRF IP solution consisting of controllers, dualmode PHY and verification environments is compliant with the latest standard specification and enables easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analog phaselocked loop (PLL) and is developed as a hard IP block to help ensure the integrity of the highspeed clocks and signals required to meet the strict timing requirements of the protocol. Available in advanced 65- and 40namometer (nm) process technologies, this highquality solution has been implemented in multiple baseband and RF IC designs.
"As a leading provider of open market ASIC solutions working with multiple foundries, sourcing highquality IP is key to our success," said Shri Gokhale, chief operating officer at Open-Silicon. "The Synopsys DesignWare 3G DigRF IP enabled us to focus on our core competencies and successfully service our customer with a product that can easily interface with leading RF ICs in the market. As one of the first members of Synopsys' IP OEM partner program, Open-Silicon is able to tightly integrate our engineers with the Synopsys IP engineering teams, allowing for a bestinclass IP integration experience for our customers."
Implemented by leading phone manufacturers, camera sensor vendors and image processor suppliers, the MIPI CSI-2 specification provides an efficient lowpower, low pin count interface between camera sensors and application processors. To meet the needs of a wide range of camera sensors ranging from economical lowend to the most demanding multimegapixel cameras, the DesignWare CSI-2 Host Controller is configurable from one to four data lanes for a total throughput of up to 4 Gbps. Complementing the CSI-2 host controller is the DesignWare MIPI D-PHY, which is a fullyintegrated hard macro available as a unidirectional or a bidirectional PHY. The unidirectional configuration is optimized to enable the implementation of very compact and low power CSI-2 host applications. The bidirectional configuration enables a single PHY to support multiple MIPI interfaces, greatly simplifying the development of designs implementing multiple MIPI interfaces such as CSI-2, DSI and UniPro. Delivering up to 1 Gbps per lane, the DesignWare MIPI D-PHY meets the bandwidth demands of today's advanced cameras and display peripherals and is siliconproven on 65nm and 40nm nodes.
"We are seeing an increasing momentum in the adoption of the MIPI Alliance interfaces standards," said Joel Huloux, chairman of the board, MIPI Alliance, Inc. "Synopsys' contribution to the different working groups and established position as a leading IP provider will help strengthen the MIPI ecosystem and further accelerate the adoption of the MIPI interfaces."
"MIPI has become the defacto industry standard for chiptochip interfaces within mobile terminals," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "With the addition of siliconproven CSI-2, DigRF and D-PHY to the DesignWare IP portfolio, designers can now turn to a single, trusted vendor to help them successfully develop innovative mobile designs using MIPI interfaces with significantly less risk."
Availability
The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller and D-PHY are available now in leading 65nm and 40nm process technologies. For more information, visit: http://www.synopsys.com/mipi
About DesignWare IP
Synopsys is a leading provider of highquality, siliconproven interface and analog IP solutions for systemonchip designs. Synopsys' broad IP portfolio delivers complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, HDMI, MIPI and Ethernet. The analog IP family includes Analogto-Digital Converters, Digitalto-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transactionlevel models to build virtual platforms for rapid, presilicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate timetomarket and reduce integration risk.
For more information on DesignWare IP, visit: http://www.synopsys.com/....
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MIPI DigRF v3 is a lowpower, low pincount interface that simplifies the integration and interoperability between the RF transceiver IC and baseband IC (BBIC). The sixpin digital interconnect reduces system cost and lowers Electromagnetic Interference (EMI) for dual and singlemode 3GPP 2.5/3G mobile terminals. The siliconproven DesignWare 3G DigRF IP solution consisting of controllers, dualmode PHY and verification environments is compliant with the latest standard specification and enables easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analog phaselocked loop (PLL) and is developed as a hard IP block to help ensure the integrity of the highspeed clocks and signals required to meet the strict timing requirements of the protocol. Available in advanced 65- and 40namometer (nm) process technologies, this highquality solution has been implemented in multiple baseband and RF IC designs.
"As a leading provider of open market ASIC solutions working with multiple foundries, sourcing highquality IP is key to our success," said Shri Gokhale, chief operating officer at Open-Silicon. "The Synopsys DesignWare 3G DigRF IP enabled us to focus on our core competencies and successfully service our customer with a product that can easily interface with leading RF ICs in the market. As one of the first members of Synopsys' IP OEM partner program, Open-Silicon is able to tightly integrate our engineers with the Synopsys IP engineering teams, allowing for a bestinclass IP integration experience for our customers."
Implemented by leading phone manufacturers, camera sensor vendors and image processor suppliers, the MIPI CSI-2 specification provides an efficient lowpower, low pin count interface between camera sensors and application processors. To meet the needs of a wide range of camera sensors ranging from economical lowend to the most demanding multimegapixel cameras, the DesignWare CSI-2 Host Controller is configurable from one to four data lanes for a total throughput of up to 4 Gbps. Complementing the CSI-2 host controller is the DesignWare MIPI D-PHY, which is a fullyintegrated hard macro available as a unidirectional or a bidirectional PHY. The unidirectional configuration is optimized to enable the implementation of very compact and low power CSI-2 host applications. The bidirectional configuration enables a single PHY to support multiple MIPI interfaces, greatly simplifying the development of designs implementing multiple MIPI interfaces such as CSI-2, DSI and UniPro. Delivering up to 1 Gbps per lane, the DesignWare MIPI D-PHY meets the bandwidth demands of today's advanced cameras and display peripherals and is siliconproven on 65nm and 40nm nodes.
"We are seeing an increasing momentum in the adoption of the MIPI Alliance interfaces standards," said Joel Huloux, chairman of the board, MIPI Alliance, Inc. "Synopsys' contribution to the different working groups and established position as a leading IP provider will help strengthen the MIPI ecosystem and further accelerate the adoption of the MIPI interfaces."
"MIPI has become the defacto industry standard for chiptochip interfaces within mobile terminals," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "With the addition of siliconproven CSI-2, DigRF and D-PHY to the DesignWare IP portfolio, designers can now turn to a single, trusted vendor to help them successfully develop innovative mobile designs using MIPI interfaces with significantly less risk."
Availability
The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller and D-PHY are available now in leading 65nm and 40nm process technologies. For more information, visit: http://www.synopsys.com/mipi
About DesignWare IP
Synopsys is a leading provider of highquality, siliconproven interface and analog IP solutions for systemonchip designs. Synopsys' broad IP portfolio delivers complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, HDMI, MIPI and Ethernet. The analog IP family includes Analogto-Digital Converters, Digitalto-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transactionlevel models to build virtual platforms for rapid, presilicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate timetomarket and reduce integration risk.
For more information on DesignWare IP, visit: http://www.synopsys.com/....
Follow us on Twitter at: http://twitter.com/....
