Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of "Groovy Green Computing: Battling the Mushrooming Use of Power."
WHO: The event is recommended for EDA tool developers, IC design engineers, and IP providers to discuss the industry-critical topics of interoperability and standards.
WHAT: The November 2009 Forum focuses on the latest developments in EDA interoperability with sessions dedicated to:
The Interoperable Process Design Kit (PDK) Libraries Alliance:
- Demonstration by key IPL Alliance members showing a single 90nm generic interoperable PDK supporting multiple vendor tools and flows including schematic capture, simulation, layout editing, physical verification and extraction
System-Level Design:
- Hear the latest developments in SystemC(tm) TLM-2.0 through the experiences of JEDA(tm) Technologies, Carbon Design Systems(tm) and Tensilica.
VMM Verification Methodology:
- Presentations from key VMM Catalyst program members on new features in VMM for verification planning and VIP, verification of low power designs, rapid testbench development and more. Attendees will receive a copy of the Doulos® Golden Reference Guide for VMM.
The Forum, with this year's theme of "Peace, Love and Interoperability," also features the most recent advances in these key EDA standards: Liberty(tm) Library Modeling, IEEE Standard 1801(tm) for Low Power, and the HapsTrak(tm) standard for prototyping board connectors.
WHEN: Thursday, November 5th in Santa Clara, Calif. The Forum is open to all who wish to attend at no cost. Lunch and a light breakfast are included.
WHERE: The Sun Conference Center at Agnews Historic Park in Santa Clara, Calif. from 9:00am to 5:00pm. For more information, directions, and to register, visit: http://www.synopsys.com/...
WHO: The event is recommended for EDA tool developers, IC design engineers, and IP providers to discuss the industry-critical topics of interoperability and standards.
WHAT: The November 2009 Forum focuses on the latest developments in EDA interoperability with sessions dedicated to:
The Interoperable Process Design Kit (PDK) Libraries Alliance:
- Demonstration by key IPL Alliance members showing a single 90nm generic interoperable PDK supporting multiple vendor tools and flows including schematic capture, simulation, layout editing, physical verification and extraction
System-Level Design:
- Hear the latest developments in SystemC(tm) TLM-2.0 through the experiences of JEDA(tm) Technologies, Carbon Design Systems(tm) and Tensilica.
VMM Verification Methodology:
- Presentations from key VMM Catalyst program members on new features in VMM for verification planning and VIP, verification of low power designs, rapid testbench development and more. Attendees will receive a copy of the Doulos® Golden Reference Guide for VMM.
The Forum, with this year's theme of "Peace, Love and Interoperability," also features the most recent advances in these key EDA standards: Liberty(tm) Library Modeling, IEEE Standard 1801(tm) for Low Power, and the HapsTrak(tm) standard for prototyping board connectors.
WHEN: Thursday, November 5th in Santa Clara, Calif. The Forum is open to all who wish to attend at no cost. Lunch and a light breakfast are included.
WHERE: The Sun Conference Center at Agnews Historic Park in Santa Clara, Calif. from 9:00am to 5:00pm. For more information, directions, and to register, visit: http://www.synopsys.com/...
