Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Exar Corporation, a provider of software and subsystem solutions for industrial, datacom and storage applications, has broadly deployed Synopsys' Design Compiler® Graphical RTL Synthesis solution, a key component of the Galaxy(TM) Implementation Platform, to shorten its IC design schedule. Previously, engineers at Exar performed multiple time-consuming iterations between synthesis and place and route due to routing congestion issues identified late in the design flow by the backend design teams. Using Design Compiler Graphical, on their latest networking IC, Exar engineers detected and fixed routing congestion hot spots early during synthesis before passing the design on for physical implementation. This allowed them to shorten their design schedule by three weeks. Consequently, Exar has made Design Compiler Graphical an integral part of its design flow in order to shorten design time across all ICs.
"Using Design Compiler Graphical's congestion analysis and optimization capabilities on our latest networking chip, we were able to address routing congestion issues during synthesis prior to place and route, enabling the design to be accomplished much faster," said Scott Peterson, division vice president of engineering design services at Exar Corporation. "With Design Compiler Graphical, a design block that would require significant effort to route was taken out of the critical path."
Design Compiler Graphical extends Synopsys' DC Ultra(TM) topographical technology to predict routing congestion hot spots early in the design flow, providing designers with visualization of congested circuitregions and allowing them to perform specialized synthesis optimizations to minimize congestion in these areas. Additionally, it provides access to the design planning capabilities of Synopsys' IC Compiler from within the synthesis environment, giving RTL designers the ability to explore and converge on an optimal floorplan faster. It also produces physical guidance to IC Compiler physical implementation, tightening timing and area correlation up to 5 percent while speeding IC Compiler placement by 1.5X. By enabling RTL designers to efficiently achieve an optimal floorplan and passing physical guidance to IC Compiler, Design Compiler Graphical doubles the productivity of the entire synthesis and place-and-route flow.
"Customers such as Exar are rapidly adopting Synopsys' Design Compiler Graphical to shorten their design schedule and stay competitive," said Bijan Kiani, vice president of product marketing, design and manufacturing products, at Synopsys. "By providing early visibility into design issues such as routing congestion, Design Compiler Graphical helps accelerate design implementation, deliver more predictable schedules and lower overall project costs."
"Using Design Compiler Graphical's congestion analysis and optimization capabilities on our latest networking chip, we were able to address routing congestion issues during synthesis prior to place and route, enabling the design to be accomplished much faster," said Scott Peterson, division vice president of engineering design services at Exar Corporation. "With Design Compiler Graphical, a design block that would require significant effort to route was taken out of the critical path."
Design Compiler Graphical extends Synopsys' DC Ultra(TM) topographical technology to predict routing congestion hot spots early in the design flow, providing designers with visualization of congested circuitregions and allowing them to perform specialized synthesis optimizations to minimize congestion in these areas. Additionally, it provides access to the design planning capabilities of Synopsys' IC Compiler from within the synthesis environment, giving RTL designers the ability to explore and converge on an optimal floorplan faster. It also produces physical guidance to IC Compiler physical implementation, tightening timing and area correlation up to 5 percent while speeding IC Compiler placement by 1.5X. By enabling RTL designers to efficiently achieve an optimal floorplan and passing physical guidance to IC Compiler, Design Compiler Graphical doubles the productivity of the entire synthesis and place-and-route flow.
"Customers such as Exar are rapidly adopting Synopsys' Design Compiler Graphical to shorten their design schedule and stay competitive," said Bijan Kiani, vice president of product marketing, design and manufacturing products, at Synopsys. "By providing early visibility into design issues such as routing congestion, Design Compiler Graphical helps accelerate design implementation, deliver more predictable schedules and lower overall project costs."
