Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it is delivering comprehensive design enablement for TSMC's 28nanometer (nm) process technology with TSMC Reference Flow 11.0. New features of the flow include solutions for systemlevel design and verification, added capabilities for 28nm design, including In-Design physical verification, and support for thrusilicon via (TSV) technology for 3D IC design. Through Reference Flow 11.0, Synopsys tools and IP enable enhanced productivity, lower power, higher yield and increased performance and integration.
"TSMC and Synopsys have a long history of collaboration on the TSMC Reference Flow," said ST Juang, senior director of design infrastructure marketing at TSMC. "The combination of Synopsys tools and IP with our 28nanometer design methodology and process technology in Reference Flow 11.0 provides engineers with comprehensive solutions that address manufacturability while enabling design for optimal performance and power consumption. The new technologies in this flow, such as thrusiliconvia and systemlevel design, bring a new level of advancement to what we offer our mutual customers."
Synopsys has extended Reference Flow 11.0 to support systemto-RTL design and verification. The addition of DesignWare® synthesizable and verification IP solutions for onchip interconnect fabric, as well as peripheral devices, enables designers to rapidly assemble systems around the AMBA® protocol. Synopsys' Innovator virtual platform tool and the DesignWare System-Level Library models provide an integrated development environment for system on chip (SoC) developers to efficiently create and debug virtual prototypes months before hardware is available, accelerating the delivery of products to market. The systemlevel solution in Reference Flow 11.0 is connected to RTL through VCS® through VMM methodology, enabling ESL testbenches and IP to be created for virtual prototypes, then reused with SystemVerilog, Verilog or VDHL.
Synopsys Galaxy(tm) Implementation Platform features complete support for TSMC's latest set of 28nm design rules in IC Compiler place and route, IC Validator physical verification, and Star-RC parasitic extraction. In-Design Physical Verification with IC Validator is a key new capability in Galaxy, enabling enhanced manufacturingcompliance and accelerated timetotapeout. In-Design Physical Verification successfully avoids latestage surprises common at advanced nodes like 28nm, by enabling IC Compiler users to do verification during physical design, assuring a manufacturingclean design at signoff. Automatic DRC Repair enabled by the IC Compiler, IC Validator combination provides an order of magnitude improvement over manual fixing of latestage DRC errors.
The Eclypse(tm) Low Power Solution includes enhanced hierarchical low power flow support with the IEEE 1801(tm) (UPF) standard. Additionally, the implementation platform now offers power management and power constraint rules. VCS with MVSIM and MVRC provide accurate simulation and static verification of designs with multirail macros, analog IP blocks and designs with complex power control architectures.
The addition of TSV support for 3D IC design to Reference Flow 11.0 provides emerging technology that complements conventional transistor scaling, allowing multiple silicon dice to be stacked and integrated in a single package. Synopsys has collaborated with TSMC in establishing a 3D stacked IC design flow that supports the vertical integration of multiple silicon dice through all stages of design, implementation, analysis and signoff.
"We've worked closely with TSMC to ensure that our design and verification platforms, as well as our low power and manufacturing compliance technologies address complex design requirements," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "The integration of enhanced systemlevel design and verification capabilities, IP and 3D IC technology offers our mutual customers an optimized path to achieve their 28nanometer SoC design goals."
About Synopsys Support for TSMC Reference Flow 11.0
TSMC Reference Flow 11.0 comprises a comprehensive set of Synopsys systemlevel, design implementation and verification tools, and IP including:
System-Level Design and AMBA Interconnect Flow
- Innovator and DesignWare System-Level Library for virtual prototyping and power/performance analysis
- DesignWare IP and Verification IP for the AMBA Interconnect provides infrastructure and fabric components for AMBA 2.0 and AMBA 3 AXI(tm). Automated assembly of the IP using coreAssembler tool.
Verification
- CustomSim(tm) and HSPICE® circuit simulation with TSMC 28nm model support
- VCS with MVSIM voltageaware simulation
- MVRC low power static checking
- ESL verification using VCS with VMM 1.2
Physical Implementation
- IC Compiler place and route, including Zroute technology and dummy via insertion
- IC Validator DRC/LVS In-Design physical verification and signoff
- PrimeRail In-Design power network analysis including VCMPaware IRdrop/EM analysis
- TSVaware floorplanning, placement and front/back side RDL routing
- TSVaware DRC/LVS physical verification
RTL Synthesis and Test
- DC Ultra(tm) and Design Compiler Graphical RTL synthesis including Topographical technology and congestion optimization
- DesignWare Library datapath IP
- Power Compiler(tm) power optimization and multivoltage power management
- Formality® equivalence checking
- DFTMAX(tm) compression for test cost reduction
- TetraMAX® automatic test pattern generation (ATPG)
Analysis and Signoff
- PrimeTime static timing analysis including advanced stagebased OCV and cell context effect analysis
- StarRC parasitic extraction with featurescale VCMP, eDRAM tall contact, viaetch and trench contact modeling support
- PrimeYield LCC for automatic lithographyhotspot and patternmatch detection and fixing, and TSMC iLPC format support
- TSVaware parasitic extraction, timing, IRdrop analysis
Synopsys Professional Services is a global member of TSMC's Design Center Alliance, providing expertise in chip implementation and flow deployment with Reference Flow 11.0. TSMC Nexsys Standard Cells and I/Os are available to DesignWare Library licensees at no additional cost.
"TSMC and Synopsys have a long history of collaboration on the TSMC Reference Flow," said ST Juang, senior director of design infrastructure marketing at TSMC. "The combination of Synopsys tools and IP with our 28nanometer design methodology and process technology in Reference Flow 11.0 provides engineers with comprehensive solutions that address manufacturability while enabling design for optimal performance and power consumption. The new technologies in this flow, such as thrusiliconvia and systemlevel design, bring a new level of advancement to what we offer our mutual customers."
Synopsys has extended Reference Flow 11.0 to support systemto-RTL design and verification. The addition of DesignWare® synthesizable and verification IP solutions for onchip interconnect fabric, as well as peripheral devices, enables designers to rapidly assemble systems around the AMBA® protocol. Synopsys' Innovator virtual platform tool and the DesignWare System-Level Library models provide an integrated development environment for system on chip (SoC) developers to efficiently create and debug virtual prototypes months before hardware is available, accelerating the delivery of products to market. The systemlevel solution in Reference Flow 11.0 is connected to RTL through VCS® through VMM methodology, enabling ESL testbenches and IP to be created for virtual prototypes, then reused with SystemVerilog, Verilog or VDHL.
Synopsys Galaxy(tm) Implementation Platform features complete support for TSMC's latest set of 28nm design rules in IC Compiler place and route, IC Validator physical verification, and Star-RC parasitic extraction. In-Design Physical Verification with IC Validator is a key new capability in Galaxy, enabling enhanced manufacturingcompliance and accelerated timetotapeout. In-Design Physical Verification successfully avoids latestage surprises common at advanced nodes like 28nm, by enabling IC Compiler users to do verification during physical design, assuring a manufacturingclean design at signoff. Automatic DRC Repair enabled by the IC Compiler, IC Validator combination provides an order of magnitude improvement over manual fixing of latestage DRC errors.
The Eclypse(tm) Low Power Solution includes enhanced hierarchical low power flow support with the IEEE 1801(tm) (UPF) standard. Additionally, the implementation platform now offers power management and power constraint rules. VCS with MVSIM and MVRC provide accurate simulation and static verification of designs with multirail macros, analog IP blocks and designs with complex power control architectures.
The addition of TSV support for 3D IC design to Reference Flow 11.0 provides emerging technology that complements conventional transistor scaling, allowing multiple silicon dice to be stacked and integrated in a single package. Synopsys has collaborated with TSMC in establishing a 3D stacked IC design flow that supports the vertical integration of multiple silicon dice through all stages of design, implementation, analysis and signoff.
"We've worked closely with TSMC to ensure that our design and verification platforms, as well as our low power and manufacturing compliance technologies address complex design requirements," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "The integration of enhanced systemlevel design and verification capabilities, IP and 3D IC technology offers our mutual customers an optimized path to achieve their 28nanometer SoC design goals."
About Synopsys Support for TSMC Reference Flow 11.0
TSMC Reference Flow 11.0 comprises a comprehensive set of Synopsys systemlevel, design implementation and verification tools, and IP including:
System-Level Design and AMBA Interconnect Flow
- Innovator and DesignWare System-Level Library for virtual prototyping and power/performance analysis
- DesignWare IP and Verification IP for the AMBA Interconnect provides infrastructure and fabric components for AMBA 2.0 and AMBA 3 AXI(tm). Automated assembly of the IP using coreAssembler tool.
Verification
- CustomSim(tm) and HSPICE® circuit simulation with TSMC 28nm model support
- VCS with MVSIM voltageaware simulation
- MVRC low power static checking
- ESL verification using VCS with VMM 1.2
Physical Implementation
- IC Compiler place and route, including Zroute technology and dummy via insertion
- IC Validator DRC/LVS In-Design physical verification and signoff
- PrimeRail In-Design power network analysis including VCMPaware IRdrop/EM analysis
- TSVaware floorplanning, placement and front/back side RDL routing
- TSVaware DRC/LVS physical verification
RTL Synthesis and Test
- DC Ultra(tm) and Design Compiler Graphical RTL synthesis including Topographical technology and congestion optimization
- DesignWare Library datapath IP
- Power Compiler(tm) power optimization and multivoltage power management
- Formality® equivalence checking
- DFTMAX(tm) compression for test cost reduction
- TetraMAX® automatic test pattern generation (ATPG)
Analysis and Signoff
- PrimeTime static timing analysis including advanced stagebased OCV and cell context effect analysis
- StarRC parasitic extraction with featurescale VCMP, eDRAM tall contact, viaetch and trench contact modeling support
- PrimeYield LCC for automatic lithographyhotspot and patternmatch detection and fixing, and TSMC iLPC format support
- TSVaware parasitic extraction, timing, IRdrop analysis
Synopsys Professional Services is a global member of TSMC's Design Center Alliance, providing expertise in chip implementation and flow deployment with Reference Flow 11.0. TSMC Nexsys Standard Cells and I/Os are available to DesignWare Library licensees at no additional cost.
