Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Silicon Image, Inc., a leading provider of semiconductors and IP for the secure distribution, presentation and storage of highdefinition content, employed DFTMAXTM compression, an integral part of the GalaxyTM Implementation Platform, to significantly lower manufacturing test cost and time. Silicon Image's mixedsignal multimedia design testing requirements included a tight form factor and a limited number of package pins. Using the new pinlimited test capability in Synopsys' DFTMAX, Silicon Image designers easily implemented test compression for the mixedsignal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.
"Because of the tight form factor of our package, only three scan inputoutput pairs were available for testing our design," said Narasimha Nookala, senior director IC engineering at Silicon Image. "DFTMAX compression for pinlimited test reduced test time and data by more than 95 percent while maintaining high defect coverage, making it a key component in the rigorous testing process we employ to deliver high quality products."
The demand for more functionality, smaller area and lower cost is leading to more stringent IC packaging constraints that limit the number of pins that can be allocated for test. In addition, to manage the complexity of large systemsonchip, designers are deploying corebased methodologies that restrict access of embedded test compression logic to only a few chiplevel pins. Multisite testing, a technique that targets multiple die simultaneously to reduce test time, is also stimulating the demand for pinlimited test because each die has access to fewer tester channels.
Synopsys recently extended DFTMAX compression to enable predictable high compression for designs and methodologies that mandate as few as one pair of test data pins. Built into the Galaxy Implementation Platform to eliminate timeconsuming iterations between synthesis, scan insertion and physical implementation, Synopsys' DFTMAX compression and TetraMAX® ATPG provide designers a comprehensive solution for meeting their most challenging quality and cost goals for test.
"Increased focus on packaging size and cost is driving the need to utilize fewer pins for manufacturing test," said Bijan Kiani, vice president of product marketing at Synopsys. "Silicon Image and other Synopsys customers are now benefiting from the superior quality of results attainable using DFTMAX compression to lower the cost of pinlimited testing."
"Because of the tight form factor of our package, only three scan inputoutput pairs were available for testing our design," said Narasimha Nookala, senior director IC engineering at Silicon Image. "DFTMAX compression for pinlimited test reduced test time and data by more than 95 percent while maintaining high defect coverage, making it a key component in the rigorous testing process we employ to deliver high quality products."
The demand for more functionality, smaller area and lower cost is leading to more stringent IC packaging constraints that limit the number of pins that can be allocated for test. In addition, to manage the complexity of large systemsonchip, designers are deploying corebased methodologies that restrict access of embedded test compression logic to only a few chiplevel pins. Multisite testing, a technique that targets multiple die simultaneously to reduce test time, is also stimulating the demand for pinlimited test because each die has access to fewer tester channels.
Synopsys recently extended DFTMAX compression to enable predictable high compression for designs and methodologies that mandate as few as one pair of test data pins. Built into the Galaxy Implementation Platform to eliminate timeconsuming iterations between synthesis, scan insertion and physical implementation, Synopsys' DFTMAX compression and TetraMAX® ATPG provide designers a comprehensive solution for meeting their most challenging quality and cost goals for test.
"Increased focus on packaging size and cost is driving the need to utilize fewer pins for manufacturing test," said Bijan Kiani, vice president of product marketing at Synopsys. "Silicon Image and other Synopsys customers are now benefiting from the superior quality of results attainable using DFTMAX compression to lower the cost of pinlimited testing."
