Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced it has signed a definitive agreement to acquire the semiconductor IP assets of MOSAID Technologies Inc. (TSX:MSD), a developer and licensor of semiconductor intellectual property. Synopsys plans to integrate such assets, consisting primarily of MOSAID's double data rate (DDR) memory controller and PHY semiconductor IP products, into its DesignWare® IP portfolio. The purchase will further increase the breadth of Synopsys' offerings in standards-based connectivity IP. The purchase price for the acquisition is approximately $15 million, payable in cash. The transaction is subject to customary closing conditions and is expected to close in August 2007.
DDR DRAM is a key component in many electronic systems manufactured today, from set-top boxes, high-definition TVs, video cameras and printers to computing, networking and communications equipment. With DDR2 DRAMs achieving speed grades up to 1067 Mbps and DDR3 DRAMs going up to 1600 Mbps, high-performance DDR interfaces become a critical factor in overall system performance. Timing and signal integrity issues can significantly complicate the design of DDR memory interfaces.
In the past, at speed grades of 500 Mbps and below, many companies have implemented the DDR interface by stitching together components such as delay-locked loops (DLLs) and phase-locked loops (PLLs). At DDR2 and DDR3 data rates, the same "roll your own" approach can cause designers to miss schedules or lower interface timing goals due to the difficulty in achieving timing closure. To better address these challenges, designers need a complete, integrated solution consisting of digital DDR memory controllers and process-specific mixed-signal DDR PHY IP that are proven to work at the required data rates.
"The addition of MOSAID's DDR memory interface IP and engineering team will give our mutual customers access to a complete, high-quality, silicon-proven DDR IP solution for a broad set of process technologies," said Joachim Kunkel, vice president and general manager, Intellectual Property and System Level Solutions, Synopsys. "With this acquisition, we continue to expand our industry-leading portfolio of standards-based connectivity IP so that our mutual customers can accelerate their time to market and minimize their design risk."
DDR2 and DDR3 memory interfaces are the latest additions to Synopsys' broad portfolio of standards-based connectivity IP. Synopsys' complete DesignWare DDR IP solution consists of digital memory controllers (protocol and memory controllers), hardened mixed-signal DDR PHYs, and verification IP. The combined product offering covers process nodes from 130nm to 65nm in today's leading foundry processes.
DDR DRAM is a key component in many electronic systems manufactured today, from set-top boxes, high-definition TVs, video cameras and printers to computing, networking and communications equipment. With DDR2 DRAMs achieving speed grades up to 1067 Mbps and DDR3 DRAMs going up to 1600 Mbps, high-performance DDR interfaces become a critical factor in overall system performance. Timing and signal integrity issues can significantly complicate the design of DDR memory interfaces.
In the past, at speed grades of 500 Mbps and below, many companies have implemented the DDR interface by stitching together components such as delay-locked loops (DLLs) and phase-locked loops (PLLs). At DDR2 and DDR3 data rates, the same "roll your own" approach can cause designers to miss schedules or lower interface timing goals due to the difficulty in achieving timing closure. To better address these challenges, designers need a complete, integrated solution consisting of digital DDR memory controllers and process-specific mixed-signal DDR PHY IP that are proven to work at the required data rates.
"The addition of MOSAID's DDR memory interface IP and engineering team will give our mutual customers access to a complete, high-quality, silicon-proven DDR IP solution for a broad set of process technologies," said Joachim Kunkel, vice president and general manager, Intellectual Property and System Level Solutions, Synopsys. "With this acquisition, we continue to expand our industry-leading portfolio of standards-based connectivity IP so that our mutual customers can accelerate their time to market and minimize their design risk."
DDR2 and DDR3 memory interfaces are the latest additions to Synopsys' broad portfolio of standards-based connectivity IP. Synopsys' complete DesignWare DDR IP solution consists of digital memory controllers (protocol and memory controllers), hardened mixed-signal DDR PHYs, and verification IP. The combined product offering covers process nodes from 130nm to 65nm in today's leading foundry processes.
