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New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces
DesignWare Universal DDR Protocol and Memory Controllers Feature a DFI 2.1-compliant Interface and Support for DDR2, DDR3, Mobile DDR and LPDDR2 Standards
The multiport DesignWare Universal DDR Memory Controller accepts memory access requests from up to 32 applicationside host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. In addition, the DesignWare Universal DDR Memory Controller provides high memory bandwidth utilization through transaction reordering, bandwidth allocation per port, and qualityofservice (QoS) based arbitration for latencysensitive and/or highbandwidth traffic.
Complementing the DesignWare DDR Universal Memory Controller, the unique singleport DesignWare Universal DDR Protocol Controller is designed to optimize memory channel bandwidth utilization with reduced latency, allowing designers to implement a custom memory scheduler that is optimized for specific DRAM traffic patterns. The DesignWare Universal DDR Protocol Controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in highspeed, general purpose process technologies and ease of timing closure in low power process technologies.
"As a fabless semiconductor company that pushes the limits of general purpose multicore processing to the highest performance per watt per silicon area, we need an established IP vendor that would enable us to optimize the throughput and latency of highend DDR memory solutions" said Peleg Aviely, CTO at Plurality Ltd. "After evaluating different IP vendors, we selected Synopsys based on their track record of delivering highquality, siliconproven DesignWare DDR IP solutions that are backed by a knowledgeable technical support team."
"As DDR SDRAM standards continue to proliferate, it is vital to provide designers with a DDR IP solution that can support the breadth of SDRAM options," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "The new DesignWare Universal DDR protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimizing the utilization of the memory channel bandwidth."
The DesignWare Universal DDR protocol and memory controllers are part of Synopsys' comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR IP supports leading 130nm, 90nm, 65nm, 55nm and 45/40nm technologies. Synopsys helps lower integration risk by providing highquality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.
Availability The DesignWare Universal DDR protocol and memory controllers as well as the complementary PHYs are available now. For more product information and video demonstrations of DesignWare DDR IP, visit: http://www.synopsys.com/ddr
About DesignWare IP
Synopsys is a leading provider of highquality, siliconproven interface and analog IP solutions for systemonchip designs. Synopsys' broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analog IP family includes Analogto-Digital Converters, Digitalto-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transactionlevel models to build virtual platforms for rapid, presilicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate timetomarket and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/.... Follow us on Twitter at http://twitter.com/....
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