Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the availability of the 2012.06 release of its IC Compiler(TM) software, featuring multiple advances to support giga-performance design. A key component of Synopsys' Galaxy(TM) Implementation Platform, IC Compiler has been addressing the productivity and manufacturability challenges inherent in giga-performance design through smarter optimization, faster design convergence and advanced process node support. This latest release of IC Compiler focuses on helping IC designers achieve higher clock frequencies more efficiently. New capabilities include innovative optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.
"Renesas Electronics is a premier provider of advanced semiconductor solutions," said Tatsuji Kagatani, department manager, Back-end Design Technology Development Department at Renesas Electronics Corporation. "We rely on continuous technology innovation in IC Compiler to realize our very challenging designs with clock speed targets of well over 1 GHz and/or lower power consumption with aggressive time to market goals. In our recent study of IC Compiler's new multisource CTS technology on a design with several complex clocks, we were easily able to meet our demanding skew and latency targets."
The IC Compiler 2012.06 release contains several new technologies geared towards boosting design frequency. Clock distribution using a mesh structure has been a staple of high performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multisource clock tree synthesis (CTS) is an innovative new technology that leverages automated clock tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.
Processor designers favor the performance scalability and smaller device geometries offered at lower process nodes. In this release, new algorithms leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. With shorter time-to-market windows and the need for a more integrated feature set, designs are seeing increasing intellectual property (IP) reuse. IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. The latest IC Compiler release can improve timing and routability for such designs. The 2012.06 release also delivers several enhancements which enable designers to achieve target frequency. Transparent interface optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power network verification and improved runtime for foundry-required metal fill insertion.
"Renesas is a dominant presence in microcontrollers and embedded SoC designs," said Michael Jackson, vice president R&D, physical implementation, Synopsys. "We have worked closely with Renesas in delivering technology enhancements to boost performance and achieve faster design closure. The results of this successful collaboration can be seen by the continued leadership of IC Compiler in the physical implementation space."
"Renesas Electronics is a premier provider of advanced semiconductor solutions," said Tatsuji Kagatani, department manager, Back-end Design Technology Development Department at Renesas Electronics Corporation. "We rely on continuous technology innovation in IC Compiler to realize our very challenging designs with clock speed targets of well over 1 GHz and/or lower power consumption with aggressive time to market goals. In our recent study of IC Compiler's new multisource CTS technology on a design with several complex clocks, we were easily able to meet our demanding skew and latency targets."
The IC Compiler 2012.06 release contains several new technologies geared towards boosting design frequency. Clock distribution using a mesh structure has been a staple of high performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multisource clock tree synthesis (CTS) is an innovative new technology that leverages automated clock tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.
Processor designers favor the performance scalability and smaller device geometries offered at lower process nodes. In this release, new algorithms leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. With shorter time-to-market windows and the need for a more integrated feature set, designs are seeing increasing intellectual property (IP) reuse. IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. The latest IC Compiler release can improve timing and routability for such designs. The 2012.06 release also delivers several enhancements which enable designers to achieve target frequency. Transparent interface optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power network verification and improved runtime for foundry-required metal fill insertion.
"Renesas is a dominant presence in microcontrollers and embedded SoC designs," said Michael Jackson, vice president R&D, physical implementation, Synopsys. "We have worked closely with Renesas in delivering technology enhancements to boost performance and achieve faster design closure. The results of this successful collaboration can be seen by the continued leadership of IC Compiler in the physical implementation space."
