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Aquantia Deploys Synopsys IC Validator and IC Compiler for 40nm Quad 10GBASE-T Design
In-Design Physical Verification Key to Accelerated Manufacturing Compliance
"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia. "IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."
Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations. Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.
With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times. For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminatethe need for costly full-chip runs.
"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys. "For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D' in DFM and handling manufacturability requirements during design instead of post-design modifications."
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