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PLS Programmierbare Logik & Systeme GmbH Straße der Freundschaft 92 02991 Lauta, Germany http://www.pls-mc.com
Contact Mr Heiko Rießland +49 35722 38438

With the UDE 3.3, PLS presents the first optimized test and debug solution for the new AURIX(TM) 32-bit multi-core MCUs

Management and control of all TriCore cores within a single user interface

(PresseBox) (Lauta (Germany), )
As a result of the very early and close cooperation with Infineon Technologies and several key customers, PLS now presents the first optimized test and debug solution, the Universal Debug Engine (UDE) 3.3, for the new multi-core architecture of the 32-bit microcontroller family AURIX.

The first AURIX architecture based microcontroller (MCU), part number TC275T, contains three TriCore processor cores (version 1.6). Two of these are optimized for maximum performance (high-performance TriCore CPU 1.6P) and can execute up to three instructions in one cycle at a maximum clock frequency of 200 MHz. With the third core, a high-efficiency TriCore CPU 1.6P, lowest possible power consumption and an efficient data exchange with the peripherals are the most important factors. It can execute a maximum of one instruction per cycle and is currently clocked at a maximum of 200 MHz.

The UDE 3.3 allows management and control of the various TriCore-CPUs within one user interface. This is supported by a flexible multicore program loader that enables the loading of program code and data as well as symbol information separately for each core. Management of the cores is carried out by a multicore run control manager, which offers a definition of core groups. Therefore, a very flexible control of the run-time behavior of the complex architecture is possible.

If required, programs for the integrated hardware security module (HSM) can also be developed with the UDE version 3.3. The HSM offers vehicle manufacturers a configurable system integrity protection of their control units and, due to its flexibility, is also equipped to meet future security requirements. In addition, the UDE 3.3 supports programming speed of the enlarged flash memory of 4 MByte by up to 20 times faster than in the previous AUDO family.

The UDE 3.3 also makes debugging of program code on the new high-performance Generic Timer Module (GTM) easier. With the help of an own instruction set, various tasks in the areas of time measurement, collection and comparison of digital input signals as well as complex algorithms such as pulse width modulation (PWM) can be solved with the GTM.

The sophisticated On-Chip Debug System (OCDS), which is well-known from the previous TriCore architecture for the AUDO family, was optimized further for the AURIX family and adapted to the requirements of multicore debugging. The new additional options are fully supported by the UDE 3.3 as well as by PLS' Universal Access Device 2 (UAD2) family and UAD3+.

Regarding program trace, data trace and bus trace, with the new AURIX architecture, Infineon again relies on the already proven Emulation Devices (ED) with integrated Multi Core Debug Solution (MCDS). The Emulation Devices are pin-compatible with the production chip. However, they contain a sophisticated observation and trigger logic as well as currently up to 2 MByte of emulation memory. Programming of the emulation logic can be comfortably carried out with the further developed Universal Emulation Configurator (UEC), which is integrated in the UDE 3.3. The reason for this is because the UEC offers a graphical configuration of measurement tasks by which signals and actions are linked by a state machine.

For the first time, Infineon has also implemented an Aurora GigaBit Trace (AGBT) interface on the Emulation Device in order to further increase testability of the new AURIX microcontroller with multi-core architecture. As a result, the trace memory can be greatly enlarged by connecting external hardware, which in turn allows the management of high-end trace tasks with large amounts of data, for example code coverage. However, a 2.5 GB/s Aurora interface requires correspondingly high-performance hardware for signal acquisition, signal conditioning and preprocessing on the target. Therefore, not only is a trace pod with AGBT interface available for the UAD3+ from PLS, but it can also be equipped with up to 4 GByte of external trace memory.

Gerd Punsmann, tool manager for 32-bit automotive microcontrollers at Infineon, explained how important the early availability of optimized test and debug tools is for the successful market introduction of high-performance multicore microcontroller families. "We want that our customers are able to start with development of applications at the day of the market introduction of our new AURIX microcontrollers with multi-core architecture. In order that this functions smoothly, a comprehensive tool environment, such as from our partner PLS, must be promptly available."

Heiko Riessland, product marketing manager at PLS, added: "The long and close cooperation between Infineon and PLS guarantees a high level of flexibility and safety for users of the AURIX microcontroller family. With availability of the first chips, users have access to a powerful and proven tool for debugging, right from the start."

PLS Programmierbare Logik & Systeme GmbH

PLS Programierbare Logik & Systeme GmbH, based in Lauta, Germany, was founded in 1990 by Thomas Bauch and Dr. Stefan Weisse. With its innovative modular test and development tools, the company has demonstrated for over two decades its position as an international technology leader in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers. The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization. Furthermore, the associated Universal Access Device (UAD2/UAD3+) product family, with transfer rates of up to 3.5 MBytes/s and a wide range of interfaces, offers entirely new dimensions for fast and flexible access to multi-core systems. Important architectures such as TriCore, Power Architecture, XC2000/XE166, ARM, Cortex, SH-2A, XScale and C166/ST10 as well as simulation platforms of different vendors are supported. For further information about the company, please visit www.pls mc.com.

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The publisher indicated in each case (see company info by clicking on image/title or company info in the right-hand column) is solely responsible for the stories above, the event or job offer shown and for the image and audio material displayed. As a rule, the publisher is also the author of the texts and the attached image, audio and information material. The use of information published here is generally free of charge for personal information and editorial processing. Please clarify any copyright issues with the stated publisher before further use. In case of publication, please send a specimen copy to service@pressebox.de.