UAD3+ sets new standards in the fields of high-end trace and multi-core/multi-target debugging

Innovative test and debugging tool for development with modern complex SoCs

UAD3+ sets new standards in the fields of high-end trace and multi-core/multi-target debugging
(PresseBox) ( Lauta (Germany), )
pls Programmierbare Logik & Systeme presents its Universal Access Device 3+ (UAD3+) in Hall 10, Booth 10-215 at embedded world 2010. This hardware tool opens up completely new possibilities for users of complex 16bit and 32bit microcontrollers (e.g. ARM7/9/11, Cortex-M3/R4/A8, PowerArchitecture, TriCore, XC2000/XE166 and SH-2A) in fields such as highend trace, multicore and multitarget debugging, profiling and calibration.

The UAD3+, a further development of the already established UAD2 family, was particularly optimized for use in multicore and multitarget systems with high clock frequencies. Thanks to the flexible pod and connector designs, up to eight various cores and targets respectively can be controlled with different debug protocols. A consistent further development of the JTAG extender technology by pls permits connection lengths of up to 5 meters to the base unit. The extenders are optionally available with galvanic electrical isolation. Furthermore, with the flexible design, the pods can also carry out tasks such as CAN interface or logic analyzer probe.

Access to the targets can take place with up to 100 MHz clock frequency optionally via various serial interfaces such as JTAG, Device Access Port (DAP) or Serial Wire Debug (SWD). Synchronization during debugging of several core/targets is achieved by the UAD3+ hardware and firmware. Two different input voltage ranges - 1.6 V to 5.5 V as standard or optionally 0.8 V to 3.3 V - cover all possible applications.

The UAD3+ from pls not only sets new standards in multicore/multitarget debugging, but also in high?end realtime trace. For this application, the highly flexible pod and connector designs ensure a simple and, at the same time, efficient support of various trace protocols (e.g. CoreSight ETM, Nexus or OCDS LII). Here too, the distance between the trace pod on the target and the base unit may also be up to 5 meters.

The recorded data can be complemented by automatically generated time stamps. With a trace memory of up to 4 GBytes, a maximal trace stream width of 32 bit and possible trace signals up to 500 MHz, the UAD3+ is also ideally equipped for future tasks.

Control of the UAD3+ takes place via pls' Universal Debug Engine (UAD) 2.7, which offers numerous functions for system visualization such as trace window, applications profiling and code coverage. Gigabit Ethernet, USB 2.0 or FireWire 800 interfaces are available as connections to the host PC.

The modular concept of the UAD3+ enables simple expansion to other architectures and debug protocols. Start of series production is planned for the second quarter of 2010.
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