Press release BoxID: 791303 (pls Programmierbare Logik & Systeme GmbH)
  • pls Programmierbare Logik & Systeme GmbH
  • Straße der Freundschaft 92
  • 02991 Lauta
  • Contact person
  • Jens Braunes
  • +49 (35722) 384-0

PLS' UDE 4.6.1 now supports NXP's latest MPC5746R Power Architecture® microcontroller

Optimized environment for debugging and test

(PresseBox) (Lauta, ) PLS Programmierbare Logik & Systeme has now introduced version 4.6.1 of its Universal Debug Engine (UDE) including a specifically optimized testing and debugging environment for MPC5746R high end multi-core controller - the newest member of NXP's Power Architecture® family.

The high performance dual-core MPC5746R System-on-Chip (SoC), optimized for automotive engine/transmission control as well as industrial applications, offers users comprehensive features to ensure the highest level of functional safety (ASIL-D). Two Power Architecture® z4 cores, running at up to 200 MHz, and the eTPU timer system meet the requirements of demanding applications. A broad selection of versions, regarding Flash sizes, core configurations and packaging options, is available for the MPC5746R.

With the UDE 4.6.1, chip internal debug functions of the MPC5746R can be completely utilized for test and debugging without any limitations. As a real multi-core debugger, UDE allows entirely controlling the dual-core MPC5746R within one single debugger framework. The UDE 4.6.1's multi-core run-control function enables an almost synchronous starting and stopping of both cores by utilizing the debug logic integrated on the chip. Additionally, multi-core breakpoints employed in shared code simplify debugging of complex applications. The breakpoint always takes effect regardless of which core is currently executing the particular code. Furthermore, freely configurable perspectives within the user interface of the UDE 4.6.1 help developers to maintain an overview in a multi-core application.

For system-level analyses, the UDE 4.6.1 provides trace-based tools, which utilize the Nexus Class 3 trace capabilities of the device. Thus, not only the program flow can be recorded for post-mortem analyses. The profiling information gained by these tools can be used for runtime optimization, for example. In addition, the UDE 4.6.1 provides the necessary code coverage to prove sufficient test coverage.

PLS' Universal Access Device 2pro (UAD2pro) and Universal Access Device 3+ (UAD3+) ensure a fast and reliable communication of the UDE 4.6.1 with the MPC5746R. Adapters matching to the specific OnCE debug interface of the Power Architecture® are available for both devices. As an option, for demanding environmental conditions, these are available with additional galvanic isolation too. Whereas the UAD2pro makes solely use of the chip's own trace memory for the Nexus trace in order to get trace data off-chip, the UAD3+ also supports the Aurora interface. With it, large amounts of trace data can be readout from the chip with transfer rates of up to 500 Mbytes/s, stored in the UAD3+ and then processed and analyzed by the UDE 4.6.1. In the UAD 3+ up to 4 GB of memory is available.

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pls Programmierbare Logik & Systeme GmbH

PLS Programierbare Logik & Systeme GmbH, based in Lauta, Germany, was founded in 1990. With its innovative modular test and development tools, the company has been one of the international technology leaders in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers for over two decades. The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization. Furthermore, the associated Universal Access Device (UAD2/UAD3+) product family, with transfer rates of up to 3.5 Mbytes/s and a wide range of interfaces, offers entirely new dimensions for fast and flexible access to multicore systems. Important architectures such as AURIX/TriCore, Power Architecture, Cortex/ARM, XC2000/XE166 as well as simulation platforms of different vendors are supported. For further information about the company, please visit www.pls