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Dedicated support for a wide range of the latest 32-bit multicore SOCs
PLS' latest Universal Debug Engine 4.0 sets new standards in the development of multicore targets(PresseBox) ( Lauta, )
With help of the newly developed target manager for the UDE 4.0, among other things, cores and functional units can now be specifically selected for debugging. In order to also be able to retain an overview with several cores, debugger window tabs and toolbars are core-specifically colored. The concept is enhanced by visibility groups for windows of individual cores or freely according to user requirements definable collections of debugger views. Furthermore, new names (alias) can be assigned freely for the window titles.
Various compiler concepts for multicore targets are supported by a newly implemented multicore / multiprogram loader. Among other things, this loader enables the separate loading of memory images and symbolic information from the output files of the compiler, specifically for each individual core.
For the control of a multicore target, the UDE 4.0 enables the synchronization of two or more cores to so‑called run control groups in order to define common start and stop or common individual step. The user interface is the same for different on-chip synchronization mechanisms. The generalized concept ensures the greatest possible flexibility when controlling a multicore target, without the need to know the underlying on-chip logic in detail.
For simple processing of the large amounts of data, which occur when tracing several sources, the UDE 4.0 is equipped with a new multicore trace framework that on the one hand allows conventional troubleshooting on the basis of the recorded data and on the other hand offers various statistical analyses such as profiling analysis and code coverage. Together with a new trace pod for PLS' Universal Access Device UAD3+, serial high-speed trace on the basis of the Aurora protocol of up to four lanes, each with 3.125 GBit/s, is supported. However, to date, currently available targets only offer one lane with 2.5 GBit/sec (AURIX/Infineon) or four lanes with 1.25 GBit/sec (Qorivva/Freescale).
For effective use of trace memory and trigger logic on so-called Emulation Devices with the UDE 4.0 the proven Universal Emulation Configurator (UEC) was enhanced for multicore architectures and support of the Signal Processing Unit (SPU) from Freescale. Programming of the additional trigger logic is performed by a graphical configuration of trace tasks, by which signals and actions are linked via a state machine.
Microcontrollers (MCUs) newly supported by the UDE 4.0 include Infineon's AURIX family, Freescale's Qorivva MPC57XX family, STMicroelectronics SPC57x family - with these three families of MCUs, programs for the integrated Generic Timer Module (GTM) and Hardware Security Module (HSM) can also be debugged - XMC4400 and XMC4200 Cortex-M4 families from Infineon as well as Hilscher's netX 51 and netX 52 network controllers.
The UDE 4.0 now offers kernel awareness for Keil / ARM RTX in accordance with the Cortex Microcontroller Software Interface Standard (CMSIS). Furthermore, the latest version of PLS' Universal Debug Engine supports the current embedded Linux versions 3.x with kernel and application debugging.
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