JTAG Technologies is pleased to announce its support - through its standard hardware and software systems - of the Altera VJI (Virtual JTAG Interface) Megafunction. Available for the majority of Altera's newer FPGA and cPLD families, the VJI Megafunction allows the JTAG (boundary-scan) test access port (TAP) to be used as a general purpose communications port for the transfer of data to an FPGA or cPLD.
Device families for which the VJI Megafunction is currently available include: ArriaR; StratixR; CycloneR; MAXR II; and APEXTM (II, 20KE and 20KC).
Peter van den Eijnden, Director JTAG Technologies comments: "By harnessing the capabilities of the VJI Megafunction, both designers and test development engineers can access the core of an FPGA or cPLD, via the JTAG port, during test and debug phases. This allows custom functionality to be introduced that facilitates much higher speed testing than is normally possible with standard JTAG/boundary-scan."
An application note covering the subject is available on request for existing JTAG customers.
Background
JTAG IEEE Std. 1149.1 boundary-scan is well known by design and test engineers alike as a mechanism for proving device-to-device connectivity at a board or system-level. In the world of programmable logic it is also widely used as the de facto method for programming configuration data into devices.
VJI Uses
While regular 'standard' JTAG tests such as scan path infrastructure, [bus-wire] interconnects, memory blocks and logic cluster tests have proved invaluable for structural testing, functional testing often relies on the completion of final product firmware.
By harnessing JTAG and the VJI Megafunction JTAG (re-)programmable FPGA cores can be designed and downloaded at test-time to implement 'at-speed' functional testing of peripheral circuits. Using JTAG Technologies' systems to implement this also facilitates test execution in a production-friendly package.
Current examples include using VJI to enhance flash memory programming performance by programming a simpler reduced BSR equivalent register. Other documented uses include the use of VJI to load and trigger BIST (Built-In Self Test) cores for ADC and DAC circuits that are accessed via an FPGA.
www.jtag.com
Device families for which the VJI Megafunction is currently available include: ArriaR; StratixR; CycloneR; MAXR II; and APEXTM (II, 20KE and 20KC).
Peter van den Eijnden, Director JTAG Technologies comments: "By harnessing the capabilities of the VJI Megafunction, both designers and test development engineers can access the core of an FPGA or cPLD, via the JTAG port, during test and debug phases. This allows custom functionality to be introduced that facilitates much higher speed testing than is normally possible with standard JTAG/boundary-scan."
An application note covering the subject is available on request for existing JTAG customers.
Background
JTAG IEEE Std. 1149.1 boundary-scan is well known by design and test engineers alike as a mechanism for proving device-to-device connectivity at a board or system-level. In the world of programmable logic it is also widely used as the de facto method for programming configuration data into devices.
VJI Uses
While regular 'standard' JTAG tests such as scan path infrastructure, [bus-wire] interconnects, memory blocks and logic cluster tests have proved invaluable for structural testing, functional testing often relies on the completion of final product firmware.
By harnessing JTAG and the VJI Megafunction JTAG (re-)programmable FPGA cores can be designed and downloaded at test-time to implement 'at-speed' functional testing of peripheral circuits. Using JTAG Technologies' systems to implement this also facilitates test execution in a production-friendly package.
Current examples include using VJI to enhance flash memory programming performance by programming a simpler reduced BSR equivalent register. Other documented uses include the use of VJI to load and trigger BIST (Built-In Self Test) cores for ADC and DAC circuits that are accessed via an FPGA.
www.jtag.com
