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Renesas Electronics Streamlines Memory Component Count in Data Center: Enables Quantity Reduction of Memory Devices to 1/15th and 60-Percent Reduction in Memory Power Consumption

Reference Design Implemented Using Renesas LLDRAM-III and FPGA Technology, Supporting Traffic in the 100-Gigabit Class

(PresseBox) (Düsseldorf, )
Renesas Electronics, a premier supplier of advanced semiconductor solutions, today announced a packet header search reference design for 100 Gigabit (Gb) communications devices such as routers, switches, and servers.

The Renesas reference design is comprised of the LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA (Note 1) device, and development support tools. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60 percent.

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