Synopsys new ultra low-power non-volatile memory IP cuts power by 90 percent and size in half
Highlights: SynopsÂys DesignWare AEON Multiple-Time Programmable Ultra Low-Power Non-Volatile Memory IP optimised f…
Highlights: SynopsÂys DesignWare AEON Multiple-Time Programmable Ultra Low-Power Non-Volatile Memory IP optimised f…
Highlights: DesignWare-ARC-HS34- und HS36-Cores sind die ersten Mitglieder der neuen Familie von High-Speed-, Low-…
. - Optimised for high efficiency, low power embedded automotive applications - Automotive Safety Integrity Level D (…
. - Integriertes, vor-verifiziertes Hardware- und Software-IP-Subsystem, bestehend aus einem leistungs- und flächen-eff…
. - Complete portfolio of data converter IP includes high speed and general purpose ADCs and DACs - New successive ap…
Highlights - First collaboration milestone speeds validation of IP and design correlation on UMC's 14nm FinFET proces…
. - Up to 3x improvement in system prototype performance enabled through enhanced HapsTrak® 3 I/O connector technology…
. - New debug flows for multiple error isolation and incremental fix capabilities enable faster implementation of large…
. - Synopsys expands its industry-leading DesignWare® DDR Memory Interface IP family to include support for DDR4 SDRAMs…
. - Full line of 28-nm DesignWare IP includes PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data convert…