81829 München, de
Xilinx is exhibitor at Embedded World 2012 in Nuremberg
You'll find the Xilinx booth in Hall 1, booth 205
Xilinx 7 Series FPGAs Power Advantage
This demonstration uses a Kintex-7 FPGA to illustrate the low total power consumption of all Xilinx 7 series FPGAs relative to previous generations and competing solutions. From up to 65% reduction in static power consumption achieved through use of the versatile 28nm high-performance, low-power process to the user-controlled power reduction innovations built into the FPGA architecture, the demonstration illustrates how users can cut their system power consumption in half, thus providing compelling evidence of Xilinx' leadership in the low-power, high-performance FPGA market.
7 Series & Zynq 7000 Agile Mixed Signal
Highlighting the value of the Analog-to-Digital Converters (ADCs) integrated into all 7 series FPGAs. The setup also shows how the signal processing capability of the FPGA enhances the ADC performance and minimizes external analog signal processing requirements. This demonstration is based on Xilinx's new AMS Evaluation Card & Software which allows users to quickly and easily evaluate the analog performance of Agile Mixed Signal.
The AMS Evaluation Card will be bundled with Kintex-7 FPGA KC705 Evaluation Kit and future 7 series kits as they become available. The set up includes an AMS Evaluation Card with external connectors and analog test signal generation, a National Instruments(TM) LabVIEW GUI for data capture and analysis, and an FPGA design.
Overall Zynq-7000 EPP demonstrations:
The Zynq-7000 EPP demonstrations to be presented at Embedded World have been selected to highlight several key messages on the Zynq-7000 EPP.
1) Zynq-7000 EPP devices are here and working well. Embedded World is the first large event where we are showing actual Zynq-7000 EPP silicon running and the first public demonstration of Zynq-7000 devices on the ZC702 development board
2) We will demonstrate the value of the tight integration of the programmable logic with the processing system, and how people can leverage this in Zynq and benefit from the extra performance that such a combination brings (Video demonstration and medical imaging example)
3) We will show the growing number of solutions offered by partners in terms of development Tools, Operating Systems and Virtual platforms.
Zynq-7000 EPP: Linux Image Processing Acceleration
This demonstration shows Linux running in SMP mode on the new Zynq-7000 EPP development board. This demo uses a floating point image processing algorithm to process a CAT scan image and render it on the screen.
The image processing is done twice: the first time in software running on the Dual Cortex-A9 processors, and the second time running the same algorithm, but with critical code segments of the image processing functions done using HW accelerators in the programmable logic. The image processing leveraging the HW accelerators in the programmable logic yields a dramatic performance improvement compared to the SW version, showing the benefit of the tight integration and the value that it brings in terms of system performance improvements.
Zynq-7000 EPP Virtual Platform for Software Development (w/ Cadence)
The Zynq virtual platform provides a functionally accurate model of the Zynq-7000 EPP processing system. It is used for porting operating systems, writing device drivers and applications. This demonstration illustrates that the virtual platform, running the same software stack as the physical hardware, can be extended to include devices or IP that are instantiated within the programmable logic. It also shows the value of a virtual platform where entire-system operation can be frozen, and every hardware register and memory address inspected for debug and development purposes.
This demonstration shows the same demonstration as the Zynq-7000 EPP Linux Image Processing Acceleration demonstration, but this time the application is running on the Zynq-7000 EPP Virtual Platform. The HW accelerators (used in the medical image processing algorithm) are implemented in the Virtual Platform using SystemC models to show the extensibility of this Virtual Platform offering and how customers can start developing their SW application on a customized Zynq-7000 EPP design even before the HW team is done with their Programmable Logic design.
Zynq-7000 EPP: HD Video Processing with HD acceleration
This is another demonstration of the value of the tight integration of the Processing System with the Programmable logic and how this can be leveraged for Video applications. Although the video processing is relatively simple, it shows that with a single solution (compared to a two chip solution) the processor can have access to the video pipeline in a way that would not be achievable in a two chip solution. Also, the tight integration means higher performance, lower power and lower cost.
Zynq-7000 EPP running Android This demo leverages the work completed by a Xilinx Customer and Partner called iVeia. It shows Android version 2.2 running on the Zynq-7000 EPP silicon with an HD video stream processed in the programmable logic, while controlled by the processing system and the output displayed in an Android graphical interface.
iVeia demonstrated Android running on the Zynq-7000 EPP Emulation platform last year at Embedded World. This year's demo shows the rapid progress that ecosystem partners have made, the value that the Zynq-7000 EPP Emulation Platform has brought in the capability to jump start partner developments and the rapidity with which they ported their solution to the final Zynq-7000 EPP Silicon
Zynq-7000 EPP: Closed-loop real time control with video object tracking
This demonstration shows a Zynq-7000 EPP device running a real-time control application. An HD video camera captures the ball's image, a fabric algorithm recognises and tracks the ball, a real-time control loop determines necessary loop corrections and provides control output to a fan motor which them appropriately adjusts the fan speed. The system tracks a second ball moved by a user and will adjust the first ball's position to match.
This demonstration is representative of some Industrial operations involving motor control and object recognition, and its main purpose is to emphasise the variety of applications that can be served with a single Zynq-7000 EPP device. It shows that through the Programmable System Integration of all these functions (Processing System with peripherals, Programmable Logic and Analog-to-digital converters) designers can create single chip solutions for many applications in cost effective, high performance and lower power flexible devices.
Zynq-7000 EPP Asymmetric Multi Processing with Linux and FreeRTOS
This demonstration shows the value of integrating two Cortex-A9 processors in a single Zynq-7000 EPP device, with one core running Linux and the other core running FreeRTOS. The value of such a solution comes from the possibility for developers to run two operating systems in parallel and dedicate one of them to run tasks - requiring low latency response to real-time events (FreeRTOS in that case).
This demo also emphasises that Xilinx is working on a comprehensive Operating System offering to meet the demand from the customers in the key market segments that Zynq-7000 EPP devices serve well, like the industrial segment in this particular case.
Zynq-7000 EPP: Lauterbach Trace32
This demonstration shows the Lauterbach Trace32 Tool connected to a Zynq-7000 EPP development board and demonstrates the debug capabilities of the Lauterbach Tools applied to the Zynq-7000 EPP devices.
This demo, along with the ARM DS5 demo also emphasises that designers can start developing their SW solutions with their favourite tool as they support the Zynq-7000 EPP devices.
Zynq-7000 EPP: ARM DS5
This demonstration shows the ARM DS5 Tool connected to a Zynq-7000 EPP development board and demonstrates the debug capabilities of the ARM tools applied to the Zynq-7000 EPP devices.
This demo, along with the Lauterbach Trace32 demo, also emphasises that designers can start developing their SW solutions with their favourite tool as they support the Zynq-7000 EPP devices.
Motor Control Targeted Design Platform
Learn how quick and easy it is to develop FPGA-based high-precision, multi-axis low noise motor control through the combination of the latest development platforms, Avnet's Spartan®-6 FPGA Motor Control Development Kit and the Motor Control IP set from Xilinx Alliance Program member, QDESYS. The Spartan-6 FPGA Motor Control Development Kit is an ideal platform for designers seeking to utilize proven reference designs, integrate high performance algorithm IP Blocks or develop custom control functionality. At the booth, Xilinx will show this targeted Motor Control Targeted Design Platform for PMSM, BLDC and stepper motors to demonstrate rapid application development as well as additional benefits such as deterministic motor performance, hardware scalability, and low EMI using sophisticated RPFM modulation.
Industrial Railcart Demo
Together with eco-system partner Prodrive, Xilinx demonstrates the capability and flexibility of the Xilinx FPGA for implementing real time industrial networking in an industrial automation system. Based on Prodrive's Four Axis Intelligent EtherCAT Drive hardware solution, this system highlights how Xilinx FPGAs enable designers to quickly integrate industrial networking interfaces into industrial automation sub-systems making them cost-effective and scalable. As well implementing real-time industrial networking, the FPGA also integrates; encoders, safety error handling/detection, current loop and modulation. This demonstration also highlights the expertise and experience offered by Prodrive in developing turnkey FPGA based systems.
Robotics Starter Kit
Xilinx eco-system partner National Instruments(TM) demonstrates the LabVIEW Robotics Starter Kit, which is enabled by Xilinx Spartan-6 FPGA. This interactive robot system which utilizes the embedded National Instruments Single-Board RIO, the Spartan-6 FPGA enables smooth robotic movement and control by decoding the on-board encoders, while also executing PID motor control algorithms, and outputting PWM signals to the robots motors in real time. In addition the FPGA handles both the data conversion from the ultrasonic sensor, so the robot detects an obstacle it will stop immediately and reliably. The National Instruments RIO architecture which includes an integrated FPGA and RTOS is an ideal platform for data acquisition and control with maximum reliability and performance.
Automotive Ethernet AVB Development Kit & IP Suite
The world's first FPGA-based, automotive-optimized Ethernet Audio/Video Bridging (EAVB) network implementation based on emerging IEEE 802.1 standards. The standards support simultaneous real time multi-camera driver assistance and audio/video entertainment. The development kit co-developed with Xilinx Alliance Program member Digital Design Corp. (DDC), gives automotive system developers a framework, including IP, hardware and tools, to meet the associated in-vehicle networking challenges of increasing digital content, required to provide a richer driver/passenger experience.
Driver Assistance Surround View Targeted Design Platform
The Driver Assistance Surround View Targeted Design Platform (TDP) provides processing for up to four camera inputs generating a 3D image of the vehicle environment from any viewing perspective.
The system can also be used as the foundation for implementation of other Driver Assistance features including rear view parking and blind spot detection. Leveraging FPGA parallel processing, multiple functions such as Surround View and Pedestrian Detection can be implemented simultaneously. In addition, FPGA reprogrammability supports cost-effective silicon re-use for features that might be mutually exclusive - for example, rear view back-up camera features at low speeds and rear-looking Land Departure Warning at higher speeds. In both cases, the same camera sensors and central processing module can be repurposed dynamically for each feature.
Stand Alone Pedestrian Detection Demonstration
Stand alone Pedestrian Detection demonstration showing the use of a single camera for real time identification of potential pedestrians, including highlighting and tracking for display purposes. Using IP from Alliance program members Xylon and eVS, the solution will show the advantages of using FPGAs in this DSP intensive application using parallel data processing on a Spartan-6 FPGA. This is a single application demonstration, but could easily be bundled in with the surround view TDP to provide an integrated solution.
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