TI delivers three high-performance clock buffer families with industry's lowest additive jitter

Reduces board footprint with small QFN and TSSOP packages

(PresseBox) ( Dallas, )
Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced three separate clock buffer families that offer improved clock signal quality with the industry's lowest additive jitter: the CDCLVC11xx, CDCLVD12xx/21xx and CDCLVP12xx/21xx families. These buffers are targeted at a variety of communication applications with frequency support of up to 2GHz (LVPECL), 800MHz (LVDS) and 250MHz (LVCMOS). These families of clock distribution buffers also save customers board space with small-footprint QFN and TSSOP options. In addition to supporting customer's general-purpose clock buffering and distribution needs, these devices also meet stringent additive jitter requirements for wireless infrastructure, data communications and telecommunications, medical imaging and industrial applications. Download datasheets, order free samples, or request evaluation modules (EVMs) here: www.ti.com/clocksandtimers-preu.

Key features and benefits of the LVCMOS, LVDS and LVPECL buffer families

1) CDCLVC11xx family for LVCMOS clock output

- Low-skew, low-additive jitter buffers generate 2, 3, 4, 6, 8, 10 and 12 copies of LVCMOS clock outputs from a single LVCMOS input.
- Very low-additive jitter of less than 100 fs RMS (12 kHz - 20 MHz) improves clock signal quality by nearly 10 times over the competition.
- Low output skew of 50 ps, maximum, provides up to five times better timing control among all outputs.
- Package modularity improves flexibility for various output configurations and simplifies board layout for multiple output requirements.

2) CDCLVD12xx/21xx family for LVDS clock output

- Generates 4, 8, 12 or 16 copies of LVDS clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.
- Very low-additive jitter of less than 300 fs RMS (10 kHz - 20 MHz) improves clock signal quality by nearly three times over the competition.
- Low output skew of 20 ps, maximum (within same bank), delivers up to 60 percent better timing control among all outputs.
- Universal input support eliminates the need for additional external discretes for signal level translation.
- Small package options in QFN-16/28/40/48 saves board space by up to 600 percent compared to competitive devices.

3) CDCLVP12xx/21xx family for LVPECL clock output

- Generates 4, 8, 12 or 16 copies of LVPECL clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.
- Very low additive jitter of less than 100 fs RMS (10 kHz - 20 MHz) improves clock signal quality by 10 times over the competition.
- Low output skew of 15/20/25/30 ps maximum for up to 40 percent better timing control among all outputs.
- Universal input support eliminates the need for additional external discretes for signal level translation.
- Small package options in QFN-16/28/40/48 saves board area by up to 600 percent compared to competitive devices.

Availability and pricing

The CDCLVC11xx, CDCLVD12xx/21xx, and CDCLVP12xx/21xx families are all available now. Suggested resale price for the 4-output version in each family is $0.90, $2.85 and $3.30, respectively, in quantities of 1,000.

Learn more about TI's Clocks and Timers portfolio

- Order free samples, request EVMs, and download datasheets: www.ti.com/clocksandtimers-preu.
- Quickly search TI's entire clocks portfolio or download the latest selection guide: www.ti.com/clocksandtimers-preu.
- Want to learn more about how clocks and timers work, watch this video: www.ti.com/pllvideo-preu.
- Ask questions and help solve problems with fellow engineers in the Clocks and Timers Forum at the TI E2E(TM) Community.
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