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Synopsys delivers comprehensive design implementation solution for Samsung's leading edge 14 nanometer FinFET process
Silicon validated solution developed through multi-year collaboration
- Close collaboration on 3-D parasitic extraction and device simulation technologies
- Industry leading place and route solution for fast design closure at 14nm geometry
- Golden reference for 14nm process development kit for IP, memory and library
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of a comprehensive design implementation solution for the Samsung 14LPE FinFET process. The solution includes new fast field solver technologies to model the effect of 3-D structures for parasitic extraction, accurate high performance models for device simulation, and comprehensive support for new rules for physical design implementation. The silicon validated solution developed under exclusive engineering collaboration accelerates adoption of the new 3-D FinFET devices for Samsung's 14nm process geometry.
"Our close collaboration with Synopsys is driven by a firm commitment to enable successful deployment of 14 nanometer FinFET technology," said Kyu-Myung Choi, senior vice president, System LSI infrastructure design center, Samsung Electronics. "With the complete, silicon-validated solution developed with Synopsys, we enable our customers to create new, innovative products by taking advantage of the power and performance benefits offered by this cutting edge 14LPE process."
"Our delivery of a comprehensive design implementation solution for Samsung's FinFET process underscores our commitment to advance the state of the art in semiconductor design," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "Deep collaboration is essential for us to address our mutual customers' FinFET needs. We have focused on foundational technologies, including 3-D parasitic extraction and device simulations, as well as delivery of FinFET ready design implementation and in-design verification tools."
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