Synopsys NanoTime Enables Full Chip Transistor Level Timing Analysis on Cavium Networks OCTEON II Internet Application Processor
Extra Precision and Coverage in Transistor-Level Timing Verification correlate within ±5% of HSPICE
"As a leader in power-efficient internet networking solutions, we require a comprehensive static timing solution that addresses both gate- and transistor-level blocks, and a quality of results that gives us a high-level of confidence that the designs have been exhaustively verified within the development timeframe," said Anil Jain, Corporate VP, IC Engineering at Cavium Networks. "NanoTime's integration with the Synopsys PrimeTime® suite provided us with extra precision and coverage in timing analysis and a comprehensive solution to achieve full-chip STA signoff."
NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis associated with custom designs. NanoTime offers concurrent timing and SI analysis with accuracy within plus-minus five percent of HSPICE, and delivers the performance required to analyze complex transistor circuits overnight. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design phase to avoid expensive silicon re-spins. Its seamless integration with Synopsys' PrimeTime product enables full-chip analysis of designs that includes both gate level and transistor-level blocks. This combination of PrimeTime and NanoTime delivers the industry's most comprehensive solution for full chip static timing signoff for today's complex systems-on-chips (SoCs).
"Cavium Networks continues to push the technology envelope in transistor-level static timing to achieve high precision silicon accuracy and verification coverage," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Synopsys is uniquely positioned to provide the stringent analysis solution that enables Cavium Networks to meet their design challenges. NanoTime not only delivers the productivity of static timing analysis to transistor-level design, but its seamless integration with Synopsys' PrimeTime suite, the industry's gold-standard for timing verification, enables a full-chip signoff solution."
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.