Synopsys NanoTime Enables Full Chip Transistor Level Timing Analysis on Cavium Networks OCTEON II Internet Application Processor

Extra Precision and Coverage in Transistor-Level Timing Verification correlate within ±5% of HSPICE

(PresseBox) ( Mountain View CA, )
Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today reported that Cavium Networks, Inc. used NanoTime transistor-level static timing analysis (STA) solution to achieve full-chip STA signoff for its next-generation internet application processor, OCTEON II that is shipping now. The multi-core, high speed OCTEON II processor is optimized for high performance network packet processing and low power consumption. Targeted for scalable networking equipment designed to fuel the voice, video and data convergence driven by cloud computing, the OCTEON II required extremely accurate timing verification in order to meet the demanding frequency target. Synopsys' NanoTime transistor-level static timing analysis (STA) solution was used extensively to deliver timing verification coverage with a degree of accuracy that correlated within plus-minus five percent of HSPICE® circuit simulator.

"As a leader in power-efficient internet networking solutions, we require a comprehensive static timing solution that addresses both gate- and transistor-level blocks, and a quality of results that gives us a high-level of confidence that the designs have been exhaustively verified within the development timeframe," said Anil Jain, Corporate VP, IC Engineering at Cavium Networks. "NanoTime's integration with the Synopsys PrimeTime® suite provided us with extra precision and coverage in timing analysis and a comprehensive solution to achieve full-chip STA signoff."

NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis associated with custom designs. NanoTime offers concurrent timing and SI analysis with accuracy within plus-minus five percent of HSPICE, and delivers the performance required to analyze complex transistor circuits overnight. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design phase to avoid expensive silicon re-spins. Its seamless integration with Synopsys' PrimeTime product enables full-chip analysis of designs that includes both gate level and transistor-level blocks. This combination of PrimeTime and NanoTime delivers the industry's most comprehensive solution for full chip static timing signoff for today's complex systems-on-chips (SoCs).

"Cavium Networks continues to push the technology envelope in transistor-level static timing to achieve high precision silicon accuracy and verification coverage," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Synopsys is uniquely positioned to provide the stringent analysis solution that enables Cavium Networks to meet their design challenges. NanoTime not only delivers the productivity of static timing analysis to transistor-level design, but its seamless integration with Synopsys' PrimeTime suite, the industry's gold-standard for timing verification, enables a full-chip signoff solution."
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