Renesas Electronics Achieves Industry's Lowest Standby Power of 13.7 nW/Mbit and 1.84 ns High-Speed Readout with New Embedded SRAM that Implements New Circuit Technology with SOTB Structure

Renesas Electronics, a premier supplier of advanced semiconductor solutions, today announced the successful development of a new low-power SRAM circuit technology that can be embedded in application specific standard products (ASSPs) for Internet of Things (IoT), home electronics, and healthcare applications. The new technology provides a function for switching dynamically, with a low power overhead, between active operation, in which the CPU core performs read and write operations of the embedded SRAM, and the standby mode, in which the stored data is retained.

Renesas applied its in-house 65 nanometer (nm) node silicon on thin BOX (SOTB, Note 1) process for the prototype development of embedded SRAM. The prototype SRAM achieves at the same time both the high-speed readout time of 1.8 ns during active operation and the ultra-low power consumption of 13.7 nW/Mbit in standby mode. The SRAM achieves the industry's lowest (Note 2) standby mode power consumption characteristics, which is only one-thousand of the power consumption during standby mode, by using dynamic substrate back bias control, taking advantage of the SOTB structure.

Recently, in the rapidly growing IoT market, all applications will be connected wirelessly, and thus there are strong desires for either battery free operation, which uses natural energy sources such as light, vibration, or heat, and lower power consumption for longer battery life. In addition, when a longer battery life is achieved, battery replacement will no longer be required, which enables applications to be maintenance free.

At the same time, achieving miniaturization of end products is essential for the development of IoT applications. Reduction of the ASSP's power consumption to at least one order of magnitude would enable miniaturization as it reduces the currently used battery capacity. As an effort to reduce the power consumption in ASSPs for the IoT, there is a technique in which the application is operated intermittently, normally being in the standby mode and only going to active mode when data processing is required. In particular, the most commonly used procedure to reduce power consumption in standby mode is to cut off power to the circuit after saving any necessary data either to an external device or to internal nonvolatile memory. Although this method is effective when wait times are relatively long, in systems that frequently iterate the switching between the active- and standby mode, the saving of data to nonvolatile memory and the restart operation becomes a significant overhead. There are even cases where, inversely, this actually increases power consumption.

The new technology adopts a method in which the power consumption of the embedded SRAM in standby mode is reduced. This enables intermittent operation to be performed frequently without leading to increased power consumption, thereby making it unnecessary to save data to nonvolatile memory, which leads to improved power efficiency.

Previous Renesas efforts related to embedded SRAM include prototype of embedded SRAM with a 28 nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16 nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies. These embedded SRAM technologies have been adopted in Renesas' R-Car automotive infotainment system-on-chips (SoCs). Now, to achieve the low-power performance required by IoT, home electronics, and healthcare applications, Renesas developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.

Key features of the new embedded SRAM technology:

1) Achieves the industry's lowest standby mode power of 13.7 nW/Mbit as well as high-speed readout operation of 1.84 ns by using substrate bias control that takes advantage of the SOTB structure Recently, the semiconductor processes miniaturization and the challenge of voltage scaling are causing issues; such as the increase in leakage current due to low threshold value of semiconductor device elements, and deterioration of operating lower limit voltage due to increasing variations in device elements.These problems result in increased power consumption in the standby mode and increased operating power due to the inability to lower operating voltages, which makes low power consumption difficult to achieve.

To respond to this issue, Renesas adopted the in-house developed SOTB process technology, which efficiently suppresses the variations between device elements and improves on/off current ratio, and has prototyped an embedded SRAM using the new technology. The SOTB process technology differs from the planar transistor structure formed on the silicon substrate in earlier process technologies as an oxide film (BOX: buried oxide) is buried under a thin silicon layer on the wafer substrate. The technology enables dopant-less channel transistors that do not require doping the thin-film silicon layer. By making the structure a dopant-less channel structure, the variations in the transistor threshold characteristics can be reduced to approximately one-third those of the earlier planar type bulk structure transistor. This reduction in variations has a similar effect to the FinFET structure adopted in state-of-the-art SoCs. Reduction of the variations in transistor performance achieves stable operation at low voltages around 0.5 V. Furthermore, adoption of a thin BOX layer in the SOTB process technology allows significant changes in threshold value characteristics of the transistors by controlling the potential of the silicon substrate under the BOX layer. This is a feature that could not be achieved with the earlier planar bulk structure or the FinFET structure. Taking advantage of this feature, Renesas provides an on-chip regulator that can dynamically control the embedded SRAM substrate bias which enables one of three operating modes (normal mode, low-power mode, and high-speed mode) or standby mode to select from according to the state of the applied substrate bias.

Using this regulator, Renesas confirmed that when high-load computational processing is required, by switching from normal mode to high-speed mode, that is, by setting the substrate potential from zero bias to a forward bias, the read access time changes from 4.58 ns to 1.84 ns, thus achieving a speed increase of 2.5 times faster compared to the normal mode. In contrast, in the standby mode, by applying a reverse bias as the substrate potential, the leakage current is reduced by three orders of magnitude to 13.7 nW/Mbit, which is only one-thousandth of the power consumption during standby mode, from the normal mode leakage power.

2) Fine-grained word line pulse width control circuit achieving up to 20 percent power reduction during active mode When the substrate bias and signal in response to the computational load are dynamically controlled, both high-speed operation and low power consumption according to the operating mode can be achieved. It is necessary to guarantee stable operation at all of the bias conditions. Even if the variations in the characteristics of the embedded SRAM are reduced when adopting the SOTB structure compared to those of the earlier planar type bulk structure devices, those variations cannot be reduced to zero. Therefore it becomes significant to secure design margins such that the memory cell with the largest variation can operate. In ASSPs for IoT applications, there are many cases where multiple SRAM macros are placed around the chip. The required design margin in each individual SRAM macro unit will vary according to the probability with which the memory cell with the largest variations is included in the macro. Conventionally, the same worst case condition design margins were assigned to each macro so that operation under worst case conditions could be reliably guaranteed for all of the macros in the chip. However, that meant that there were always macros for which the margins were excessive.

To improve this situation, Renesas proposed a replica circuit method in which the read pulse width could be optimized in a fine-grained (Note 3) manner to target removal of those excessive design margins. This makes it possible to reduce the active power by up to 20 percent during read operations.

The low-power embedded SRAM achieves both the low standby mode power consumption and increased operating speed, which were difficult to achieve with the continuing progress of the semiconductor process miniaturization. By enabling ASSPs that adopt the embedded SRAM with SOTB structure, Renesas plans to support both energy harvesting operation and contributing to the development of maintenance free IoT applications that do not require battery replacement. Furthermore, by including the embedded SRAM in low-power ASSPs that are fabricated using the 65 nm SOTB process, Renesas plans to further contribute to the creation of a smarter society.

At the VLSI Symposia 2017, Renesas presented the results of this effort on June 8 which was held in Kyoto, Japan, from June 5-9, 2017.

Note 1: BOX: buried oxide

Note 2: As of June 8, 2017, according to Renesas research

Note 3: In small macro units