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Olympus-ITA 3D-IC Metrology System Verifies Alignment for 3D Interconnects in Bonded Wafers
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The 3D interconnect process using TSVs requires bonding the active side of processed wafers together. Once the wafers are bonded there is an immediate need to verify the accuracy of the bonding alignment, but the active wafer surfaces containing the alignment targets are no longer visible. The Olympus IR 3D-IC Metrology System allows observation and image acquisition of the alignment targets and vias by "seeing" through up to 1200µm of bulk silicon to the patterned surfaces. Overlaid alignment marks are imaged and measured to verify bonding alignment accuracy. IR microscopy is a nondestructive technique, making it especially suited to inline metrology for the bonded wafer pairs and dies required for 3D interconnects.
"As has been previously presented by Andrew Rudack of SEMATECH*, IR microscopy can be used as an early indicator of electrical yield in bonded wafer pairs used for 3D integration," said Greg Baker, Olympus-ITA president. "Overlay metrology using IR microscopy can immediately follow the wafer bonding process and be used to predict yields at this early stage in the 3D interconnect process, providing substantial savings in manufacturing costs."
Olympus-ITA will also present a paper with SEMATECH and the College of Nanoscale Science and Engineering, University at Albany titled IR Microscopy for Overlay and Defect Metrology of 3D Interconnect Bonded Wafers. The paper will be part of the Advanced Metrology session at the ASMC Technical Conference on Tuesday, July 13, 2010 at the San Francisco Marriott in San Francisco, CA. ASMC is held in conjunction with SEMICON West which is being held from July 13-15 at the Moscone Convention Center, San Francisco.
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