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Raising the Profile of Testability/ Optimise your ATE
Design for Testability (DfT)
The DfT challenge is the ‘Cinderella’ of the design process. Overcoming this challenge is not as exciting as designing and proving a new solution. Yet, DfT/testability should not be overlooked. A design that addresses testability without requiring add-ons that compromise the original scheme is every bit as fulfilling as seeing the first prototype roll off the production line. After all, without adequate testability, that new assembly’s debut will be delayed by revisions and, possibly even, reworking.
Ideally, a new board design can be debugged using software tools completely before the first prototype is built. Unfortunately, though, we do not leave in an ideal world and obscure design bugs tend to appear only after the hardware is built.
The reasons for testability challenges are many-fold and all are a consequence of advances in electronics design. The drive to miniaturize all designs, means that components are placed close together with fine-pitch interconnects and the latest chip-scale-packages (CSPs) do not make it easy to probe I/Os hidden beneath the component.
JTAG Technologies believes that only an integrated test strategy offers a solution. Come and see us at Embedded world and we show you the latest Boundary Scan solutions.
And Optimise your ATE
What test engineers worry about these days: the access to nodes of assemblies with ever increasing complexity is more and more difficult and results in reduced fault coverage.
JTAG Technologies’ main motto for Embedded World 2016 year reads: Optimise your ATE with JTAG Technologies Inside — come and take a look at the test possibilities that arise from the use of “JTAG TECHNOLOGIES INSIDE” and see the current test methods and possibilities from a different perspective. In our booth at Embedded World we will display the following highlights from our comprehensive ATE product portfolio:
ICT, MDA or flying probe systems are quickly and easily upgraded with JTAG Technologies’ boundary-scan solutions. Special add-on cards and software integration suites enable users to benefit from the features of the combined systems.
Traditional functional tests based on National Instruments’ LabView/TestStand, C++, .net and other programming languages often feature complex and time-consuming test programs. Easy access to your assembly via boundary-scan pins can simplify your existing test programs and ease diagnosis in case of faults.
Peter van den Eijnden, managing director of JTAG Technologies commented this year’s focus for the Embedded World show: “For many years we have been cooperating with renowned ATE suppliers to make sure that our customers will continue to enjoy optimal use of their existing ICT/MDA/FPT/FCT systems throughout the coming years. In joint efforts with several test system manufacturers we have developed special hardware and software solutions. These special solutions enable perfect integration of our tools into these test systems, so users benefit from advantages of the combination of both methods”.
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