EU-funded SYNAPTIC project delivers state of the art design synthesis tool flow
The SYNAPTIC research project includes eight partner organisations from across Europe who have joined forces to develop new regularity-centric design methods and related EDA tools. The goal is to reduce limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography.
At the heart of the SYNAPTIC project is the development of regularity-aware synthesis methodologies, first at the architectural level, then at the synthesis level, and finally in layout generation and the subsequent integration of the new methods into EDA tools.
State-of-the-art Design Synthesis Tool Flow
Martin Elhøj, SYNAPTIC Project Coordinator and VP R&D with NanGate, explains that the consortium has completed the integration of new state of the art design synthesis algorithms and methodologies developed in the project into a prototype EDA tool build on top of Nangate's Design Optimizer product. The synthesis tool identifies functionality which, if added to the base synthesis library, enables further optimisation of critical design metrics. The additional functionality is then automatically implemented as new standard cells using the SYNAPTIC RDR layout generation tool based on Nangate's Library Creator product. The design specific functions are created from highly optimized Boolean expressions aiming to reduce transistor count when compared to the same functionality implemented using multiple standard cells. This approach has consistently shown more than 20% reduction in transistor count for medium size compound cells and the design resynthesis utilizing the extended cell set provides area improvements not available with current EDA tools while maintaining other critical design metrics. In this way the impact on area imposed by Restricted Design Rules is reduced thus enabling the creation of competitive designs employing regularity techniques to reduce variability and improve yield. Although the tools are in the prototype stage they already demonstrate very good results and further optimizations are the target of the third and final year of the project.
Layout Styles and Restricted Design Rules effectively reduces Variability
The project has developed two unique layout styles and sets of restricted design rules; (1) ALARC for strict 1D routing and (2) 2D Gridded allowing 2D M1 routing while keeping all other layers 1D. The two structures have been demonstrated to significantly reduce the variations of drawn transistor length and width when compared to traditional layout styles. This reduces the overall variability of a design, and thus enables designers to reduce the guard bands that have become common in today's design methodology.
To confirm that the proposed RDR rules and layout styles are feasible candidates to be deployed in industrial designs where SRAM is commonplace, the consortium has designed three SRAM bit cell layouts and compared the Figure of Merits (FOM) against a state-of-the-art high density SRAM cell. The results confirm that it is indeed feasible to create SRAM cells with comparable FOM using the regular layout styles.
Measurement of layout regularity is a critical aspect in regularity-centric design creation and to quickly assess the level of regularity without the need for compute intensive and expensive litho simulation tools, the consortium has developed a fast regularity metric; ARMLE (Algorithm of Regularity Metric for Layout Evaluation). This metric enables the qualitative comparison of different layout styles with respect to regularity
Meet SYNAPTIC at DATE2012 and DAC2012
SYNPATIC project is the co-organizer of the Friday workshop, VAMM, at DATE 2012 in Dresden, Germany on March 16, 2012. The workshop will focus on design techniques to counteract the problem of variability. Techniques may range from the device level, to layout design, to architecture design. They include the use of redundancy, regularity and reconfiguration at different description levels.
The SYNAPTIC project will showcase its design synthesis tool flow during DAC 2012 in San Francisco, CA. from June 4 to June 6 2012.
Consortium partners include design optimization company Nangate, Europe's largest IDM, STMicroelectronics; Thales (France), which is the European global technology leader for the aerospace, space, defence, security and transportation markets; and imec(Belgium), which performs world-leading research in nanoelectronics. Three leading universities, Politecnico di Milano (Italy), Universitat Politècnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) bring significant and highly specialised technology contributions to the joint research. The final partner, Leading Edge, is participating as a consultancy company specialising in the introduction of innovative EDA technologies to the European marketplace.
NanGate, a provider of physical intellectual property (IP) and a leader in Electronic Design Automation (EDA) software, offers tools and services for creation and validation of physical library IP, and analysis and optimization of digital design. NanGate's suite of solutions includes Library Creation Platform, NanGate Design Optimizer, MegaLibrary IP, and professional services. NanGate's solution enables IC design to optimize in performance and power, while significantly reducing area and cost. The solution, as a complement to existing design flows, deliver results that previously can only be achieved with resource intensive custom design techniques.
NanGate is headquartered in Sunnyvale, California, and has offices in Denmark and Russia. Visit NanGate online at http://www.nangate.com
ST is a global leader in the semiconductor market serving customers across the spectrum of sense and power technologies and multimedia convergence applications. From energy management and savings to trust and data security, from healthcare and wellness to smart consumer devices, in the home, car and office, at work and at play, ST is found everywhere microelectronics make a positive and innovative contribution to people's life. By getting more from technology to get more from life, ST stands for life.augmented.
In 2011, the Company's net revenues were $9.73 billion. Further information on ST can be found at www.st.com.
Thales is a global technology leader for the Defence & Security and the Aerospace & Transport markets. In 2011, the company generated revenues of €13 billion with 68,000 employees in more than 50 countries. With its 22,500 engineers and researchers, Thales has a unique capability to design, develop and deploy equipment, systems and services that meet the most complex security requirements. Thales has an exceptional international footprint, with operations around the world working with customers as local partners.
Thales believes innovation is key in mastering complexity. Ideas that can make a real difference are being made possible through dynamic, open partnerships with key universities, SMEs and international research laboratories.
Thales develops strategic capabilities in component, software and system engineering and architectures through its Research & Technology (R&T) organisation. For example, this organization develops innovative solutions along the information chain exploiting sensors data, through expertise in computational architectures in embedded systems, mathematics and technologies for decision involving information fusion and cognitive processing, and model driven engineering.
A key mission of Thales Research & Technology centres is bi-directional transfer between scientific research and the corresponding businesses. Benefiting from its presence and visibility on the international scene in advanced sciences, technology and software, Thales R&T is perceived as a valuable partner of the best research centres (academic or industrial) through recognised scientists and research engineer participation in collaborative projects.
About Politecnico di Milano:
The Politecnico di Milano is one of the largest Italian engineering universities, ranked among the best fifteen technology universities in Europe in the Times Higher Education-QS World University Rankings. This project involves personnel of the Embedded systems design and design methodologies of the Dipartimento di Elettronica e Informazione, composed of 4 full professors, 6 associate professors, and a number of assistant professors and PhD students. The research group has long been active in the field of designing computer architectures and developing methodologies and prototype tools to support the automation of different phases of design of advanced embedded systems.
About Universitat Politècnica de Catalunya:
UPC is one of the main technical universities in Spain. It is specialised in the areas of engineering, science and architecture. It has around 30,000 undergraduate students and 4,000 graduate students (PhD and Master). It has a teaching staff of nearly 3,000. The UPC participation in the SYNAPTIC project is through the research group "High Performance Integrated Circuits and Systems Design Group" (HIPICS), in the Department of Electronic Engineering. With more than 15 years of experience, this research group has covered several areas of research: design and test techniques for integrated circuits, energy harvesting, design of CMOS RF circuits, and design techniques for integrated circuits tolerant to noise and process variations.
About Universidade Federal do Rio Grande do Sul:
UFRGS is one of the largest Brazilian universities, ranking in top positions for graduate and undergraduate courses in Computer Science, Computer Engineering and Microelectronics. This project involves personnel of the Group of Computational Tools for Integrated Circuit Design of the Instituto de Informática, composed of 2 professors, and around 15 researchers divided into Post-doc grantees, PhD students, MsC1 students and undergraduate students. The research group has long been active in the field of computational tools for integrated circuit design, especially at the cell level where the group developed a unique competence in switch theory and transistor network generation and evaluation.
About Leading Edge:
Leading Edge is a privately held company specialising in the introduction of innovative EDA technologies to the European marketplace. Leading Edge was formed in 2005 and benefits from the considerable EDA experience gained by the founders while working for major players in the EDA arena such as Synopsys, Mentor Graphics and Magma Design Automation. Leading Edge provides technical consulting and commercial services to a number of European and US-based EDA startups. Leading Edge also provides training courses on various design-related topics and is a certified training center for Mentor Graphics and a member of the Altera Training Partner Program.
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of about 1,900 people includes more than 500 industrial residents and guest researchers. In 2010, imec's revenue (P&L) was 285 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut"), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.) and imec India (Imec India Private Limited).