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Renesas Electronics Streamlines Memory Component Count in Data Center: Enables Quantity Reduction of Memory Devices to 1/15th and 60-Percent Reduction in Memory Power Consumption
Reference Design Implemented Using Renesas LLDRAM-III and FPGA Technology, Supporting Traffic in the 100-Gigabit Class
The Renesas reference design is comprised of the LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA (Note 1) device, and development support tools. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60 percent.
With the arrival of the Internet of Things (IoT) era and the rapid increase in the volume of data flowing to and from connected devices, increasing network speeds has become a priority. In particular, more data centers are switching their traffic speeds from 40 Gb to 100 Gb to support the increasing volume of data, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Also, widespread adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. Against this background, Renesas has developed a power-efficient packet header search reference design able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries.
Key features of the packet header search reference design:
1) Packet header search of one million entries or more (Note 2) in 100Gb traffic using only two watts of power, equivalent to power consumption of 40Gb traffic
LLDRAM-III is a power-efficient type of low-latency memory from Renesas that supports 400 mega accesses (read or write operations) per second and consumes two watts or less to transfer 57.6 Gb of data. By combining this memory with the newly-developed search algorithm from Renesas, it is possible to process 150 million packet header searches per second, as required for 100 Gb Ethernet, using a single LLDRAM-III device. Performing the same processing with a configuration using a conventional search algorithm (Note 3) and standard DRAM would require around 15 memory devices and consume about five watts of power (Note 4). The new reference design reduces the number of memory devices to a single LLDRAM-III memory and cuts memory power consumption by 60 percent. This shrinks the memory mounting area by 90 percent and also reduces the number of signal lines between the memory and FPGA by 90 percent, making it possible to configure the system using an FPGA with fewer pins and contributing to reduced overall cost.
2) Flexible search key length functionality that eliminates the need for modifications to the search IP design to accommodate new communication protocols
The exact-match search IP allows the flexibility of changing the search key length in one-bit units up to a maximum of 143 bits (Note 5). This makes it possible to accommodate not only conventional MAC address searches but also new communication protocols made possible by advances in network virtualization technology without having to modify the search IP design. Also, the number of search entries can be expanded to two million or even four million by specifying a shorter maximum search key (Note 6) length. This also includes functionality that supports simultaneous output of search results and packet processing rules when the maximum search key length of 143 bits is used, by dividing the search key area and the packet processing rule area appended to the search result.
3) Fully integrated reference design kit can shorten development time needed for designing network equipment by approximately six months
The development support tools consist of 1) a reference board with proven interoperability between the FPGA and LLDRAM-III, thereby saving time that would otherwise be needed for design and verification, 2) sample design including search IP, 3) a complete verification environment, and 4) a complete evaluation environment. These tools enable users to begin FPGA subsystem design and network equipment design work in parallel, which significantly reduces the development cycle time by around six months (according to calculations by Renesas).
Renesas provides NSEs (https://www.renesas.com/en-hq/about/press-center/news/2015/news20150427.html) for the complex communication processing at the 200-Gb class used by external communication interfaces of data centers and backbone communication networks. For communication processing at 100 Gb and below, in applications within data centers having large numbers of ports, Renesas provides a packet header search reference design composed of LLDRAM-III and FPGA. With this new FPGA-based search solution that enables flexible communication and support for rapidly-advancing network technology, Renesas continues its commitment to the communications market with the development of new solutions.
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