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SLAC National Accelerator Laboratory Selects Corelis
Corelis Boundary-Scan Tools Reduce Prototype Debug Time(PresseBox) ( Cerritos, )
The RCE circuit board modules are currently used to store detector data collected during proton collisions traveling near the speed of light in the twomile linear accelerator at the University of Stanford. The technology is also being considered for the Very Large Telescope (VLT) Array in Chilé, the Large Hadron Collider (LHC) at the CERN research center of the Swiss/French border, and the Large Synoptic Survey Telescope (LSST) in Chilé which will study Dark Matter and Dark Energy.
Prior to boundaryscan testing, O'Grady was limited to probing circuit board test points with an oscilloscope resulting in an average debug time of two days for each problematic board. Now with boundaryscan testing, the debug time has been reduced to about one minute, or roughly the time it takes to set up a board and run the boundaryscan test.
O'Grady explained, "Two days of troubleshooting per board is excessive, especially when highly skilled personnel need to be involved. When five boards are bad, two weeks of my time is tied up causing major delays on other projects. It simply got to a point where we needed to either reduce the debug time or assign the task to someone else."
"The Corelis tools have allowed me to recover lost time. When five boards have problems, not only do Corelis tools save me two weeks worth of work, but I can deliver five boards that much faster!"
About SLAC National Accelerator Laboratory
SLAC National Accelerator Laboratory is a multiprogram laboratory exploring frontier questions in photon science, astrophysics, particle physics, and accelerator research. Located in Menlo Park, California, SLAC is operated by Stanford University for the U.S. Department of Energy Office of Science.
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