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Agilent Technologies Introduces Electrical Retimer Solution to Solve Key Challenges in Designing Chip-to-Chip Links
The retimer solution, available in the Advanced Design System 2013
Transient Convolution Element and SystemVue 2013 AMI Modeling Kit, is used for designing electrical retimers in chip-to-chip, high-speed digital links.
Before the multigigabit era, chip-to-chip digital signals propagated across entire printed circuit boards with little distortion. However, at today's speeds, rising and falling edges degrade after traveling only a few inches on production board materials like FR4. In digital applications, it is cost-prohibitive to use high-frequency laminate board materials to solve the problem. A more economical solution is to insert a mid-channel retimer circuit.
Up to now, simulation tools used to design in these nonlinear devices have used computationally expensive SPICE techniques like Newton-Raphson iteration on modified nodal analysis of Kirchoff's current law. With this latest breakthrough, Agilent offers a quick solution based on bit-by-bit channel simulation and the IBIS AMI flow to retimer applications. Unlike SPICE, these techniques include computationally efficient algorithms like superposition.
Using a prestandard, novel extension to the industry-standard IBIS AMI flow, SystemVue 2013 now offers model builders (typically integrated circuit vendors) a tool to build retimer models. The models run in ADS, the tool that IC consumers (typically data center and telecoms equipment manufacturers) use to design these chips into their systems.
"With our previous repeater model library release we added a simpler class of repeater models called redrivers," said Colin Warwick, product manager for High-Speed Digital Design at Agilent EEsof EDA. "In general, retimers are more complex because they include additional circuitry for clock/data recovery. Our new retimer models join the existing redriver models to form a complete library of repeaters. We're working with leading retimer and redriver IC vendors to make these models available to mutual customers."
Agilent will submit a proposed enhancement to the IBIS Open Forum later this year. The intent is to incorporate the new techniques into a future version of the IBIS standard. This will ensure retimer model portability across EDA tools in future.
In addition, ADS 2013 adds support for power-aware IBIS models and for the Touchstone 2 file format, as well as a Touchstone Combiner that lets engineers build multiport victim/aggressor channel models out of measured data from a four-port vector network analyzer.
Agilent's SystemVue 2013 and Advanced Design System 2013 are available now. A schematic showing the retimer model in use is available at www.agilent.com/find/ADS_RetimerModeling_images.
Agilent offers a wide selection of high-speed digital solutions including essential tools to pinpoint problems, optimize devices and deliver results for design and simulation.
Agilent will demonstrate its retimer solution, along with solutions that range from circuit-level modeling through system verification for general RF, microwave, 4G communications, and aerospace/defense applications, at IMS 2013/IEEE MTT-S (Booth 1230), June 2-7, in Seattle. A range of premier partner solutions will also be available on Agilent Avenue and throughout the event area.
About Agilent EEsof EDA Software
Agilent EEsof EDA is the leading supplier of electronic design automation software for microwave, RF, high-frequency, high-speed digital, RF system, electronic system level, circuit, 3-D electromagnetic, physical design and device-modeling applications. More information is available at www.agilent.com/find/eesof.
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