Agilent Technologies Announces Industry-First Compliance Test Suite for DDR4 and LPDDR3 Logic Analysis
Now Digital Designers Can Customize Tests, Monitor Protocol Violations in Real Time for Digital Memory Applications(PresseBox) (Santa Clara, Calif., )
The new software allows users to customize tests, either by adding to existing test groups or by defining unique test groups of valid logic analyzer triggers for protocol or bus-level timing violations. Customized real-time compliance tests can be defined for any valid logic analyzer trigger, for any digital system probed by an Agilent logic analyzer.
“Our customers who work with computer and embedded memory systems have asked for a way to identify and track protocol and bus-level timing issues as they occur, rather than only validating after the trace is captured,” said Perry Keller, memory program manager of Agilent’s Electronic Test Division. “With this new compliance test suite, our customers can quickly identify design problems, allowing them to get products into the marketplace more quickly.”
Keller is Agilent’s representative on the JEDEC DDR memory standards committee.
The protocol debug and validation test suite includes three products:
- Agilent B4621B, a bus decoder for DDR/2/3/4
- Agilent B4622B, a protocol compliance and analysis toolset for DDR/2/3/4 and LPDDR/2/3
- Agilent B4623B, a bus decoder for LPDDR/2/3
The B4621B bus decoder for DDR/2/3/4 debug and validation provides complete protocol decoding of memory transactions using an Agilent logic analyzer as the execution engine. The protocol-decoding software translates acquired signals into easily understood colorized bus transactions showing associated data bursts for double-edge data-rate captures up to 2.5 Gb/s.
The B4622B DDR/2/3/4 and LPDDR/2/3 protocol compliance and analysis toolset is the industry’s only protocol compliance toolset and the industry’s first automated, real-time compliance application for DDR4 and LPDDR3. It automatically captures real-time compliance protocol violations, detects post-process protocol violations on captured traces, takes performance measurements, and creates physical address triggers.
The B4623B bus decoder for LPDDR/2/3 debugging and validation is a complete protocol decoder of memory transactions for LPDDR/2/3 using an Agilent logic analyzer as the execution engine. The software translates acquired signals into easily understood bus transactions showing associated data bursts, for all LPDDR2/3 data rates. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command.
Agilent will showcase its new compliance test suite for computer and embedded DDR/2/3/4 and LPDDR/2/3 memory applications at the 2012 Intel Developer Forum (Booth 721), Sept. 11-14 in San Francisco and at Memcon 2012 (Booth 10), Sept. 18 in Santa Clara, Calif.
Additional information about Agilent’s compliance test suite for protocol debug and validation is available at:
A high-resolution screen image of Agilent’s compliance test suite for DDR4 and LPDDR3 logic analysis is available at www.agilent.com/find/B4621B_B4622B_B4623B_images.