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China's Tsinghua University Selects Advantest's T5830ES and T5833ES Semiconductor Memory Testers for Educational Purposes
Top Academic Institution in China Will Use Advantest's Systems as Unique Platforms to Train Students for Developing Memory Technology
“We are pleased to continue our working partnership with Tsinghua University, which has substantial influence in the Chinese semiconductor ecosystem and helps to demonstrate our testers’ capabilities for China’s design houses,” said Xu Yong, CEO of Advantest China. “Our test solutions for advanced memories are being used throughout China to address high-growth markets including the Internet of Things and smart cards.”
The T5830ES memory tester is an engineering system optimized for highly cost-effective testing of a wide range of flash memory devices. This versatile platform is designed to provide a high return on investment (ROI) and reduce users’ financial risk. It is capable of handling data transfer rates as high as 800 megabits per second (Mbps).
A scalable, built-in high-current programmable power supply (PPS) architecture enables the system to perform wafer sorting and final testing of both low-pin-count and high-pin-count flash memories. Like other members of the T5800 product family, it is built using Advantest’s innovative Tester-per-Site™ design, which allows each site to operate independently for very fast test times and a lower overall cost of test, and it leverages FutureSuite™ software for enhanced reliability and upgradeability.
Advantest’s multifunctional T5833ES engineering station is designed for both wafer sorting and final testing for a full range of memory ICs including LPDDR3 DRAMs, high-speed NAND flash devices and next-generation non-volatile memories. In addition to supporting known good die (KGD) testing at speeds up to 2.4 gigabits per second (Gbps), the T5833ES also features a flexible site CPU architecture with multiple CPUs for optimal control of test processes.
The system offers industry-leading capabilities in high-speed failure address storage and failure analysis, also known as memory redundancy. Both of these operations are scalable by making adjustments such as adding more CPUs for calculations.
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