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Advantest to Sponsor and Participate in 50th International Test Conference in Washington, DC, November 12-14
Test Industry Market Leader to Exhibit Newest IC and AI Test Solutions and Feature Prominently in ITC's Renowned Technical Program
Advantest is once again a platinum-level corporate supporter of ITC as well as a sponsor of the 50th Celebration on the evening of November 12 and the Test Technology Technical Council’s (TTTC) Automotive Reliability and Test (ART) Workshop on November 14-15.
Advantest’s booth #209 will feature demonstrations of its on-demand CloudTesting™ Service, the latest capabilities of its EVA 100 low-cost analog/digital IC test solution, a new EVA stimulus tester for automotive current sensors, and a new tool that combines cloud and real-time edge-computing artificial intelligence (AI).
The innovative, first-of-its-kind CloudTesting Service allows users to access various test-method IP selections on Advantest’s website whenever needed. Using this on-demand online service, designers can verify their new silicon at a very low cost with no capital investment, set up their own test environments within a few hours and be ready to test when the device arrives from the fab. With free tester leasing and minimum maintenance costs, Advantest’s CloudTesting Service allows customers to avoid unplanned expenses.
Advantest’s EVA100 analog/mixed-signal test solution combines a modular architecture with high-voltage and high-precision analog parametric measurement units, providing the flexibility to conduct various measurements over a broad range of analog and mixed-signal devices. The versatile, small-footprint EVA100 tester is easy to use for device characterization through volume production. The scalable architecture can be quickly reconfigured to address a varied product portfolio and achieve lower cost benefits from economies of scale.
In addition to product exhibits, Advantest experts will discuss the latest test technologies over the course of ITC’s technical program with the following presentations and posters:
Wednesday, November 13, 11:30 a.m. to 1:30 p.m. in Exhibit Hall
PO 4: In-Test Flow Neural Network Inference on the V93000 SmarTest Test Cell Controller
M. Eiki, K. Schaub, I. Leventhal, B. Buras
PO 5: CloudTesting™ Service Enables Board-Level Post-Silicon Debug
R. Radhakrishnan, A. Kashyap, S. Panigatti, Y. Oyama, A. Sivaram
PO 7: High-Volume Consumer Devices Need High-Voltage Test Solution
A. Lum, B. Wang, R. Waikar, A. Sivaram
PO 49: An Effective INL Test Methodology for Low-Sampling-Rate and High-Resolution Analog-to-Digital Converter
K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, H. Kobayashi, K. Hatayama, T. Nakatani, A. Kuwana, J-L. Wei, N. Kushita, H. Arai, L. Sha
Monday, November 11, 2:00 p.m. in Washington 4
Test Challenges Meeting Hosted by Jeff Rearick, AMD
Shifting Left for True KGD
Wednesday, November 13, 3:00 p.m. to 4:30 p.m. in Washington 2
Paper 8.3: A Jitter Injection Module for Production Test of 52-Gbps PAM-4 Signal Interfaces
K. Ichiyama, T. Kusaka, M. Ishida
Wednesday, November 13, 3:00 p.m. to 4:30 p.m. in Washington 4
Paper 10.3: A New Test Method for Large-Current Magnetic Sensors
T. Omuro, S. Nakamura, T. Kimura, T. Kiyokawa
IPP2 2.4: Subtle Anomaly Detection of Microscopic Probes Using Deep Learning-based Image Completion
K. Schaub, I. Leanthal, K. Ikeda, Advantest and Y. Makris, C. Xanthopoulos, D. Neethirajan, The University of Texas at Dallas
Thursday, November 14, 1:30 p.m. to 3:00 p.m. in Washington 2
Panel: Roadblocks for the Hetrogeneous Integration Roadmap in Test
D. Armstrong, Panelist
Thursday, November 14, 3:00 p.m. to 4:30 p.m. in Ballroom
Invited Visionary Talk: Semiconductor Test – Towards a Data Driven Futur
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